/***************************************************************************//**
* \file cyreg_tcpwm.h
*
* \brief
* TCPWM register definition header
*
* \note
* Generator version: 1.5.0.1299
* Database revision: TVIIBH4M_WW1937_for_CFR_MetalTO
*
********************************************************************************
* \copyright
* Copyright 2016-2019, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/

#ifndef _CYREG_TCPWM_H_
#define _CYREG_TCPWM_H_

#include "cyip_tcpwm_v2.h"

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT0)
  */
#define CYREG_TCPWM0_GRP0_CNT0_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580000UL)
#define CYREG_TCPWM0_GRP0_CNT0_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580004UL)
#define CYREG_TCPWM0_GRP0_CNT0_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580008UL)
#define CYREG_TCPWM0_GRP0_CNT0_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580010UL)
#define CYREG_TCPWM0_GRP0_CNT0_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580014UL)
#define CYREG_TCPWM0_GRP0_CNT0_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580018UL)
#define CYREG_TCPWM0_GRP0_CNT0_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058001CUL)
#define CYREG_TCPWM0_GRP0_CNT0_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580020UL)
#define CYREG_TCPWM0_GRP0_CNT0_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580024UL)
#define CYREG_TCPWM0_GRP0_CNT0_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580030UL)
#define CYREG_TCPWM0_GRP0_CNT0_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580040UL)
#define CYREG_TCPWM0_GRP0_CNT0_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580044UL)
#define CYREG_TCPWM0_GRP0_CNT0_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580048UL)
#define CYREG_TCPWM0_GRP0_CNT0_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058004CUL)
#define CYREG_TCPWM0_GRP0_CNT0_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580050UL)
#define CYREG_TCPWM0_GRP0_CNT0_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580054UL)
#define CYREG_TCPWM0_GRP0_CNT0_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580070UL)
#define CYREG_TCPWM0_GRP0_CNT0_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580074UL)
#define CYREG_TCPWM0_GRP0_CNT0_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580078UL)
#define CYREG_TCPWM0_GRP0_CNT0_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058007CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT1)
  */
#define CYREG_TCPWM0_GRP0_CNT1_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580080UL)
#define CYREG_TCPWM0_GRP0_CNT1_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580084UL)
#define CYREG_TCPWM0_GRP0_CNT1_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580088UL)
#define CYREG_TCPWM0_GRP0_CNT1_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580090UL)
#define CYREG_TCPWM0_GRP0_CNT1_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580094UL)
#define CYREG_TCPWM0_GRP0_CNT1_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580098UL)
#define CYREG_TCPWM0_GRP0_CNT1_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058009CUL)
#define CYREG_TCPWM0_GRP0_CNT1_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405800A0UL)
#define CYREG_TCPWM0_GRP0_CNT1_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405800A4UL)
#define CYREG_TCPWM0_GRP0_CNT1_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405800B0UL)
#define CYREG_TCPWM0_GRP0_CNT1_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405800C0UL)
#define CYREG_TCPWM0_GRP0_CNT1_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405800C4UL)
#define CYREG_TCPWM0_GRP0_CNT1_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405800C8UL)
#define CYREG_TCPWM0_GRP0_CNT1_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405800CCUL)
#define CYREG_TCPWM0_GRP0_CNT1_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405800D0UL)
#define CYREG_TCPWM0_GRP0_CNT1_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405800D4UL)
#define CYREG_TCPWM0_GRP0_CNT1_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405800F0UL)
#define CYREG_TCPWM0_GRP0_CNT1_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405800F4UL)
#define CYREG_TCPWM0_GRP0_CNT1_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405800F8UL)
#define CYREG_TCPWM0_GRP0_CNT1_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405800FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT2)
  */
#define CYREG_TCPWM0_GRP0_CNT2_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580100UL)
#define CYREG_TCPWM0_GRP0_CNT2_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580104UL)
#define CYREG_TCPWM0_GRP0_CNT2_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580108UL)
#define CYREG_TCPWM0_GRP0_CNT2_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580110UL)
#define CYREG_TCPWM0_GRP0_CNT2_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580114UL)
#define CYREG_TCPWM0_GRP0_CNT2_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580118UL)
#define CYREG_TCPWM0_GRP0_CNT2_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058011CUL)
#define CYREG_TCPWM0_GRP0_CNT2_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580120UL)
#define CYREG_TCPWM0_GRP0_CNT2_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580124UL)
#define CYREG_TCPWM0_GRP0_CNT2_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580130UL)
#define CYREG_TCPWM0_GRP0_CNT2_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580140UL)
#define CYREG_TCPWM0_GRP0_CNT2_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580144UL)
#define CYREG_TCPWM0_GRP0_CNT2_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580148UL)
#define CYREG_TCPWM0_GRP0_CNT2_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058014CUL)
#define CYREG_TCPWM0_GRP0_CNT2_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580150UL)
#define CYREG_TCPWM0_GRP0_CNT2_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580154UL)
#define CYREG_TCPWM0_GRP0_CNT2_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580170UL)
#define CYREG_TCPWM0_GRP0_CNT2_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580174UL)
#define CYREG_TCPWM0_GRP0_CNT2_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580178UL)
#define CYREG_TCPWM0_GRP0_CNT2_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058017CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT3)
  */
#define CYREG_TCPWM0_GRP0_CNT3_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580180UL)
#define CYREG_TCPWM0_GRP0_CNT3_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580184UL)
#define CYREG_TCPWM0_GRP0_CNT3_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580188UL)
#define CYREG_TCPWM0_GRP0_CNT3_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580190UL)
#define CYREG_TCPWM0_GRP0_CNT3_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580194UL)
#define CYREG_TCPWM0_GRP0_CNT3_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580198UL)
#define CYREG_TCPWM0_GRP0_CNT3_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058019CUL)
#define CYREG_TCPWM0_GRP0_CNT3_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405801A0UL)
#define CYREG_TCPWM0_GRP0_CNT3_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405801A4UL)
#define CYREG_TCPWM0_GRP0_CNT3_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405801B0UL)
#define CYREG_TCPWM0_GRP0_CNT3_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405801C0UL)
#define CYREG_TCPWM0_GRP0_CNT3_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405801C4UL)
#define CYREG_TCPWM0_GRP0_CNT3_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405801C8UL)
#define CYREG_TCPWM0_GRP0_CNT3_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405801CCUL)
#define CYREG_TCPWM0_GRP0_CNT3_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405801D0UL)
#define CYREG_TCPWM0_GRP0_CNT3_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405801D4UL)
#define CYREG_TCPWM0_GRP0_CNT3_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405801F0UL)
#define CYREG_TCPWM0_GRP0_CNT3_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405801F4UL)
#define CYREG_TCPWM0_GRP0_CNT3_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405801F8UL)
#define CYREG_TCPWM0_GRP0_CNT3_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405801FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT4)
  */
#define CYREG_TCPWM0_GRP0_CNT4_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580200UL)
#define CYREG_TCPWM0_GRP0_CNT4_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580204UL)
#define CYREG_TCPWM0_GRP0_CNT4_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580208UL)
#define CYREG_TCPWM0_GRP0_CNT4_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580210UL)
#define CYREG_TCPWM0_GRP0_CNT4_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580214UL)
#define CYREG_TCPWM0_GRP0_CNT4_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580218UL)
#define CYREG_TCPWM0_GRP0_CNT4_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058021CUL)
#define CYREG_TCPWM0_GRP0_CNT4_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580220UL)
#define CYREG_TCPWM0_GRP0_CNT4_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580224UL)
#define CYREG_TCPWM0_GRP0_CNT4_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580230UL)
#define CYREG_TCPWM0_GRP0_CNT4_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580240UL)
#define CYREG_TCPWM0_GRP0_CNT4_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580244UL)
#define CYREG_TCPWM0_GRP0_CNT4_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580248UL)
#define CYREG_TCPWM0_GRP0_CNT4_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058024CUL)
#define CYREG_TCPWM0_GRP0_CNT4_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580250UL)
#define CYREG_TCPWM0_GRP0_CNT4_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580254UL)
#define CYREG_TCPWM0_GRP0_CNT4_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580270UL)
#define CYREG_TCPWM0_GRP0_CNT4_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580274UL)
#define CYREG_TCPWM0_GRP0_CNT4_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580278UL)
#define CYREG_TCPWM0_GRP0_CNT4_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058027CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT5)
  */
#define CYREG_TCPWM0_GRP0_CNT5_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580280UL)
#define CYREG_TCPWM0_GRP0_CNT5_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580284UL)
#define CYREG_TCPWM0_GRP0_CNT5_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580288UL)
#define CYREG_TCPWM0_GRP0_CNT5_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580290UL)
#define CYREG_TCPWM0_GRP0_CNT5_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580294UL)
#define CYREG_TCPWM0_GRP0_CNT5_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580298UL)
#define CYREG_TCPWM0_GRP0_CNT5_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058029CUL)
#define CYREG_TCPWM0_GRP0_CNT5_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405802A0UL)
#define CYREG_TCPWM0_GRP0_CNT5_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405802A4UL)
#define CYREG_TCPWM0_GRP0_CNT5_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405802B0UL)
#define CYREG_TCPWM0_GRP0_CNT5_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405802C0UL)
#define CYREG_TCPWM0_GRP0_CNT5_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405802C4UL)
#define CYREG_TCPWM0_GRP0_CNT5_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405802C8UL)
#define CYREG_TCPWM0_GRP0_CNT5_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405802CCUL)
#define CYREG_TCPWM0_GRP0_CNT5_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405802D0UL)
#define CYREG_TCPWM0_GRP0_CNT5_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405802D4UL)
#define CYREG_TCPWM0_GRP0_CNT5_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405802F0UL)
#define CYREG_TCPWM0_GRP0_CNT5_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405802F4UL)
#define CYREG_TCPWM0_GRP0_CNT5_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405802F8UL)
#define CYREG_TCPWM0_GRP0_CNT5_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405802FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT6)
  */
#define CYREG_TCPWM0_GRP0_CNT6_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580300UL)
#define CYREG_TCPWM0_GRP0_CNT6_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580304UL)
#define CYREG_TCPWM0_GRP0_CNT6_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580308UL)
#define CYREG_TCPWM0_GRP0_CNT6_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580310UL)
#define CYREG_TCPWM0_GRP0_CNT6_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580314UL)
#define CYREG_TCPWM0_GRP0_CNT6_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580318UL)
#define CYREG_TCPWM0_GRP0_CNT6_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058031CUL)
#define CYREG_TCPWM0_GRP0_CNT6_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580320UL)
#define CYREG_TCPWM0_GRP0_CNT6_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580324UL)
#define CYREG_TCPWM0_GRP0_CNT6_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580330UL)
#define CYREG_TCPWM0_GRP0_CNT6_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580340UL)
#define CYREG_TCPWM0_GRP0_CNT6_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580344UL)
#define CYREG_TCPWM0_GRP0_CNT6_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580348UL)
#define CYREG_TCPWM0_GRP0_CNT6_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058034CUL)
#define CYREG_TCPWM0_GRP0_CNT6_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580350UL)
#define CYREG_TCPWM0_GRP0_CNT6_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580354UL)
#define CYREG_TCPWM0_GRP0_CNT6_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580370UL)
#define CYREG_TCPWM0_GRP0_CNT6_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580374UL)
#define CYREG_TCPWM0_GRP0_CNT6_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580378UL)
#define CYREG_TCPWM0_GRP0_CNT6_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058037CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT7)
  */
#define CYREG_TCPWM0_GRP0_CNT7_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580380UL)
#define CYREG_TCPWM0_GRP0_CNT7_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580384UL)
#define CYREG_TCPWM0_GRP0_CNT7_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580388UL)
#define CYREG_TCPWM0_GRP0_CNT7_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580390UL)
#define CYREG_TCPWM0_GRP0_CNT7_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580394UL)
#define CYREG_TCPWM0_GRP0_CNT7_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580398UL)
#define CYREG_TCPWM0_GRP0_CNT7_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058039CUL)
#define CYREG_TCPWM0_GRP0_CNT7_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405803A0UL)
#define CYREG_TCPWM0_GRP0_CNT7_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405803A4UL)
#define CYREG_TCPWM0_GRP0_CNT7_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405803B0UL)
#define CYREG_TCPWM0_GRP0_CNT7_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405803C0UL)
#define CYREG_TCPWM0_GRP0_CNT7_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405803C4UL)
#define CYREG_TCPWM0_GRP0_CNT7_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405803C8UL)
#define CYREG_TCPWM0_GRP0_CNT7_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405803CCUL)
#define CYREG_TCPWM0_GRP0_CNT7_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405803D0UL)
#define CYREG_TCPWM0_GRP0_CNT7_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405803D4UL)
#define CYREG_TCPWM0_GRP0_CNT7_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405803F0UL)
#define CYREG_TCPWM0_GRP0_CNT7_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405803F4UL)
#define CYREG_TCPWM0_GRP0_CNT7_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405803F8UL)
#define CYREG_TCPWM0_GRP0_CNT7_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405803FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT8)
  */
#define CYREG_TCPWM0_GRP0_CNT8_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580400UL)
#define CYREG_TCPWM0_GRP0_CNT8_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580404UL)
#define CYREG_TCPWM0_GRP0_CNT8_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580408UL)
#define CYREG_TCPWM0_GRP0_CNT8_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580410UL)
#define CYREG_TCPWM0_GRP0_CNT8_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580414UL)
#define CYREG_TCPWM0_GRP0_CNT8_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580418UL)
#define CYREG_TCPWM0_GRP0_CNT8_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058041CUL)
#define CYREG_TCPWM0_GRP0_CNT8_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580420UL)
#define CYREG_TCPWM0_GRP0_CNT8_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580424UL)
#define CYREG_TCPWM0_GRP0_CNT8_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580430UL)
#define CYREG_TCPWM0_GRP0_CNT8_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580440UL)
#define CYREG_TCPWM0_GRP0_CNT8_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580444UL)
#define CYREG_TCPWM0_GRP0_CNT8_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580448UL)
#define CYREG_TCPWM0_GRP0_CNT8_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058044CUL)
#define CYREG_TCPWM0_GRP0_CNT8_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580450UL)
#define CYREG_TCPWM0_GRP0_CNT8_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580454UL)
#define CYREG_TCPWM0_GRP0_CNT8_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580470UL)
#define CYREG_TCPWM0_GRP0_CNT8_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580474UL)
#define CYREG_TCPWM0_GRP0_CNT8_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580478UL)
#define CYREG_TCPWM0_GRP0_CNT8_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058047CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT9)
  */
#define CYREG_TCPWM0_GRP0_CNT9_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580480UL)
#define CYREG_TCPWM0_GRP0_CNT9_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580484UL)
#define CYREG_TCPWM0_GRP0_CNT9_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580488UL)
#define CYREG_TCPWM0_GRP0_CNT9_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580490UL)
#define CYREG_TCPWM0_GRP0_CNT9_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580494UL)
#define CYREG_TCPWM0_GRP0_CNT9_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580498UL)
#define CYREG_TCPWM0_GRP0_CNT9_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058049CUL)
#define CYREG_TCPWM0_GRP0_CNT9_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405804A0UL)
#define CYREG_TCPWM0_GRP0_CNT9_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405804A4UL)
#define CYREG_TCPWM0_GRP0_CNT9_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405804B0UL)
#define CYREG_TCPWM0_GRP0_CNT9_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405804C0UL)
#define CYREG_TCPWM0_GRP0_CNT9_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405804C4UL)
#define CYREG_TCPWM0_GRP0_CNT9_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405804C8UL)
#define CYREG_TCPWM0_GRP0_CNT9_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405804CCUL)
#define CYREG_TCPWM0_GRP0_CNT9_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405804D0UL)
#define CYREG_TCPWM0_GRP0_CNT9_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405804D4UL)
#define CYREG_TCPWM0_GRP0_CNT9_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405804F0UL)
#define CYREG_TCPWM0_GRP0_CNT9_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405804F4UL)
#define CYREG_TCPWM0_GRP0_CNT9_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405804F8UL)
#define CYREG_TCPWM0_GRP0_CNT9_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405804FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT10)
  */
#define CYREG_TCPWM0_GRP0_CNT10_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580500UL)
#define CYREG_TCPWM0_GRP0_CNT10_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580504UL)
#define CYREG_TCPWM0_GRP0_CNT10_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580508UL)
#define CYREG_TCPWM0_GRP0_CNT10_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580510UL)
#define CYREG_TCPWM0_GRP0_CNT10_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580514UL)
#define CYREG_TCPWM0_GRP0_CNT10_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580518UL)
#define CYREG_TCPWM0_GRP0_CNT10_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058051CUL)
#define CYREG_TCPWM0_GRP0_CNT10_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580520UL)
#define CYREG_TCPWM0_GRP0_CNT10_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580524UL)
#define CYREG_TCPWM0_GRP0_CNT10_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580530UL)
#define CYREG_TCPWM0_GRP0_CNT10_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580540UL)
#define CYREG_TCPWM0_GRP0_CNT10_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580544UL)
#define CYREG_TCPWM0_GRP0_CNT10_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580548UL)
#define CYREG_TCPWM0_GRP0_CNT10_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058054CUL)
#define CYREG_TCPWM0_GRP0_CNT10_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580550UL)
#define CYREG_TCPWM0_GRP0_CNT10_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580554UL)
#define CYREG_TCPWM0_GRP0_CNT10_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580570UL)
#define CYREG_TCPWM0_GRP0_CNT10_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580574UL)
#define CYREG_TCPWM0_GRP0_CNT10_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580578UL)
#define CYREG_TCPWM0_GRP0_CNT10_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058057CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT11)
  */
#define CYREG_TCPWM0_GRP0_CNT11_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580580UL)
#define CYREG_TCPWM0_GRP0_CNT11_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580584UL)
#define CYREG_TCPWM0_GRP0_CNT11_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580588UL)
#define CYREG_TCPWM0_GRP0_CNT11_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580590UL)
#define CYREG_TCPWM0_GRP0_CNT11_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580594UL)
#define CYREG_TCPWM0_GRP0_CNT11_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580598UL)
#define CYREG_TCPWM0_GRP0_CNT11_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058059CUL)
#define CYREG_TCPWM0_GRP0_CNT11_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405805A0UL)
#define CYREG_TCPWM0_GRP0_CNT11_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405805A4UL)
#define CYREG_TCPWM0_GRP0_CNT11_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405805B0UL)
#define CYREG_TCPWM0_GRP0_CNT11_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405805C0UL)
#define CYREG_TCPWM0_GRP0_CNT11_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405805C4UL)
#define CYREG_TCPWM0_GRP0_CNT11_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405805C8UL)
#define CYREG_TCPWM0_GRP0_CNT11_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405805CCUL)
#define CYREG_TCPWM0_GRP0_CNT11_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405805D0UL)
#define CYREG_TCPWM0_GRP0_CNT11_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405805D4UL)
#define CYREG_TCPWM0_GRP0_CNT11_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405805F0UL)
#define CYREG_TCPWM0_GRP0_CNT11_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405805F4UL)
#define CYREG_TCPWM0_GRP0_CNT11_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405805F8UL)
#define CYREG_TCPWM0_GRP0_CNT11_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405805FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT12)
  */
#define CYREG_TCPWM0_GRP0_CNT12_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580600UL)
#define CYREG_TCPWM0_GRP0_CNT12_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580604UL)
#define CYREG_TCPWM0_GRP0_CNT12_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580608UL)
#define CYREG_TCPWM0_GRP0_CNT12_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580610UL)
#define CYREG_TCPWM0_GRP0_CNT12_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580614UL)
#define CYREG_TCPWM0_GRP0_CNT12_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580618UL)
#define CYREG_TCPWM0_GRP0_CNT12_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058061CUL)
#define CYREG_TCPWM0_GRP0_CNT12_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580620UL)
#define CYREG_TCPWM0_GRP0_CNT12_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580624UL)
#define CYREG_TCPWM0_GRP0_CNT12_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580630UL)
#define CYREG_TCPWM0_GRP0_CNT12_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580640UL)
#define CYREG_TCPWM0_GRP0_CNT12_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580644UL)
#define CYREG_TCPWM0_GRP0_CNT12_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580648UL)
#define CYREG_TCPWM0_GRP0_CNT12_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058064CUL)
#define CYREG_TCPWM0_GRP0_CNT12_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580650UL)
#define CYREG_TCPWM0_GRP0_CNT12_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580654UL)
#define CYREG_TCPWM0_GRP0_CNT12_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580670UL)
#define CYREG_TCPWM0_GRP0_CNT12_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580674UL)
#define CYREG_TCPWM0_GRP0_CNT12_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580678UL)
#define CYREG_TCPWM0_GRP0_CNT12_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058067CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT13)
  */
#define CYREG_TCPWM0_GRP0_CNT13_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580680UL)
#define CYREG_TCPWM0_GRP0_CNT13_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580684UL)
#define CYREG_TCPWM0_GRP0_CNT13_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580688UL)
#define CYREG_TCPWM0_GRP0_CNT13_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580690UL)
#define CYREG_TCPWM0_GRP0_CNT13_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580694UL)
#define CYREG_TCPWM0_GRP0_CNT13_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580698UL)
#define CYREG_TCPWM0_GRP0_CNT13_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058069CUL)
#define CYREG_TCPWM0_GRP0_CNT13_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405806A0UL)
#define CYREG_TCPWM0_GRP0_CNT13_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405806A4UL)
#define CYREG_TCPWM0_GRP0_CNT13_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405806B0UL)
#define CYREG_TCPWM0_GRP0_CNT13_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405806C0UL)
#define CYREG_TCPWM0_GRP0_CNT13_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405806C4UL)
#define CYREG_TCPWM0_GRP0_CNT13_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405806C8UL)
#define CYREG_TCPWM0_GRP0_CNT13_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405806CCUL)
#define CYREG_TCPWM0_GRP0_CNT13_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405806D0UL)
#define CYREG_TCPWM0_GRP0_CNT13_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405806D4UL)
#define CYREG_TCPWM0_GRP0_CNT13_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405806F0UL)
#define CYREG_TCPWM0_GRP0_CNT13_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405806F4UL)
#define CYREG_TCPWM0_GRP0_CNT13_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405806F8UL)
#define CYREG_TCPWM0_GRP0_CNT13_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405806FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT14)
  */
#define CYREG_TCPWM0_GRP0_CNT14_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580700UL)
#define CYREG_TCPWM0_GRP0_CNT14_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580704UL)
#define CYREG_TCPWM0_GRP0_CNT14_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580708UL)
#define CYREG_TCPWM0_GRP0_CNT14_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580710UL)
#define CYREG_TCPWM0_GRP0_CNT14_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580714UL)
#define CYREG_TCPWM0_GRP0_CNT14_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580718UL)
#define CYREG_TCPWM0_GRP0_CNT14_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058071CUL)
#define CYREG_TCPWM0_GRP0_CNT14_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580720UL)
#define CYREG_TCPWM0_GRP0_CNT14_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580724UL)
#define CYREG_TCPWM0_GRP0_CNT14_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580730UL)
#define CYREG_TCPWM0_GRP0_CNT14_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580740UL)
#define CYREG_TCPWM0_GRP0_CNT14_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580744UL)
#define CYREG_TCPWM0_GRP0_CNT14_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580748UL)
#define CYREG_TCPWM0_GRP0_CNT14_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058074CUL)
#define CYREG_TCPWM0_GRP0_CNT14_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580750UL)
#define CYREG_TCPWM0_GRP0_CNT14_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580754UL)
#define CYREG_TCPWM0_GRP0_CNT14_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580770UL)
#define CYREG_TCPWM0_GRP0_CNT14_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580774UL)
#define CYREG_TCPWM0_GRP0_CNT14_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580778UL)
#define CYREG_TCPWM0_GRP0_CNT14_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058077CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT15)
  */
#define CYREG_TCPWM0_GRP0_CNT15_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580780UL)
#define CYREG_TCPWM0_GRP0_CNT15_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580784UL)
#define CYREG_TCPWM0_GRP0_CNT15_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580788UL)
#define CYREG_TCPWM0_GRP0_CNT15_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580790UL)
#define CYREG_TCPWM0_GRP0_CNT15_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580794UL)
#define CYREG_TCPWM0_GRP0_CNT15_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580798UL)
#define CYREG_TCPWM0_GRP0_CNT15_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058079CUL)
#define CYREG_TCPWM0_GRP0_CNT15_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405807A0UL)
#define CYREG_TCPWM0_GRP0_CNT15_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405807A4UL)
#define CYREG_TCPWM0_GRP0_CNT15_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405807B0UL)
#define CYREG_TCPWM0_GRP0_CNT15_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405807C0UL)
#define CYREG_TCPWM0_GRP0_CNT15_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405807C4UL)
#define CYREG_TCPWM0_GRP0_CNT15_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405807C8UL)
#define CYREG_TCPWM0_GRP0_CNT15_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405807CCUL)
#define CYREG_TCPWM0_GRP0_CNT15_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405807D0UL)
#define CYREG_TCPWM0_GRP0_CNT15_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405807D4UL)
#define CYREG_TCPWM0_GRP0_CNT15_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405807F0UL)
#define CYREG_TCPWM0_GRP0_CNT15_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405807F4UL)
#define CYREG_TCPWM0_GRP0_CNT15_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405807F8UL)
#define CYREG_TCPWM0_GRP0_CNT15_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405807FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT16)
  */
#define CYREG_TCPWM0_GRP0_CNT16_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580800UL)
#define CYREG_TCPWM0_GRP0_CNT16_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580804UL)
#define CYREG_TCPWM0_GRP0_CNT16_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580808UL)
#define CYREG_TCPWM0_GRP0_CNT16_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580810UL)
#define CYREG_TCPWM0_GRP0_CNT16_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580814UL)
#define CYREG_TCPWM0_GRP0_CNT16_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580818UL)
#define CYREG_TCPWM0_GRP0_CNT16_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058081CUL)
#define CYREG_TCPWM0_GRP0_CNT16_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580820UL)
#define CYREG_TCPWM0_GRP0_CNT16_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580824UL)
#define CYREG_TCPWM0_GRP0_CNT16_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580830UL)
#define CYREG_TCPWM0_GRP0_CNT16_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580840UL)
#define CYREG_TCPWM0_GRP0_CNT16_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580844UL)
#define CYREG_TCPWM0_GRP0_CNT16_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580848UL)
#define CYREG_TCPWM0_GRP0_CNT16_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058084CUL)
#define CYREG_TCPWM0_GRP0_CNT16_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580850UL)
#define CYREG_TCPWM0_GRP0_CNT16_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580854UL)
#define CYREG_TCPWM0_GRP0_CNT16_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580870UL)
#define CYREG_TCPWM0_GRP0_CNT16_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580874UL)
#define CYREG_TCPWM0_GRP0_CNT16_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580878UL)
#define CYREG_TCPWM0_GRP0_CNT16_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058087CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT17)
  */
#define CYREG_TCPWM0_GRP0_CNT17_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580880UL)
#define CYREG_TCPWM0_GRP0_CNT17_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580884UL)
#define CYREG_TCPWM0_GRP0_CNT17_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580888UL)
#define CYREG_TCPWM0_GRP0_CNT17_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580890UL)
#define CYREG_TCPWM0_GRP0_CNT17_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580894UL)
#define CYREG_TCPWM0_GRP0_CNT17_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580898UL)
#define CYREG_TCPWM0_GRP0_CNT17_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058089CUL)
#define CYREG_TCPWM0_GRP0_CNT17_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405808A0UL)
#define CYREG_TCPWM0_GRP0_CNT17_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405808A4UL)
#define CYREG_TCPWM0_GRP0_CNT17_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405808B0UL)
#define CYREG_TCPWM0_GRP0_CNT17_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405808C0UL)
#define CYREG_TCPWM0_GRP0_CNT17_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405808C4UL)
#define CYREG_TCPWM0_GRP0_CNT17_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405808C8UL)
#define CYREG_TCPWM0_GRP0_CNT17_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405808CCUL)
#define CYREG_TCPWM0_GRP0_CNT17_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405808D0UL)
#define CYREG_TCPWM0_GRP0_CNT17_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405808D4UL)
#define CYREG_TCPWM0_GRP0_CNT17_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405808F0UL)
#define CYREG_TCPWM0_GRP0_CNT17_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405808F4UL)
#define CYREG_TCPWM0_GRP0_CNT17_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405808F8UL)
#define CYREG_TCPWM0_GRP0_CNT17_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405808FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT18)
  */
#define CYREG_TCPWM0_GRP0_CNT18_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580900UL)
#define CYREG_TCPWM0_GRP0_CNT18_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580904UL)
#define CYREG_TCPWM0_GRP0_CNT18_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580908UL)
#define CYREG_TCPWM0_GRP0_CNT18_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580910UL)
#define CYREG_TCPWM0_GRP0_CNT18_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580914UL)
#define CYREG_TCPWM0_GRP0_CNT18_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580918UL)
#define CYREG_TCPWM0_GRP0_CNT18_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058091CUL)
#define CYREG_TCPWM0_GRP0_CNT18_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580920UL)
#define CYREG_TCPWM0_GRP0_CNT18_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580924UL)
#define CYREG_TCPWM0_GRP0_CNT18_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580930UL)
#define CYREG_TCPWM0_GRP0_CNT18_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580940UL)
#define CYREG_TCPWM0_GRP0_CNT18_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580944UL)
#define CYREG_TCPWM0_GRP0_CNT18_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580948UL)
#define CYREG_TCPWM0_GRP0_CNT18_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058094CUL)
#define CYREG_TCPWM0_GRP0_CNT18_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580950UL)
#define CYREG_TCPWM0_GRP0_CNT18_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580954UL)
#define CYREG_TCPWM0_GRP0_CNT18_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580970UL)
#define CYREG_TCPWM0_GRP0_CNT18_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580974UL)
#define CYREG_TCPWM0_GRP0_CNT18_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580978UL)
#define CYREG_TCPWM0_GRP0_CNT18_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058097CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT19)
  */
#define CYREG_TCPWM0_GRP0_CNT19_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580980UL)
#define CYREG_TCPWM0_GRP0_CNT19_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580984UL)
#define CYREG_TCPWM0_GRP0_CNT19_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580988UL)
#define CYREG_TCPWM0_GRP0_CNT19_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580990UL)
#define CYREG_TCPWM0_GRP0_CNT19_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580994UL)
#define CYREG_TCPWM0_GRP0_CNT19_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580998UL)
#define CYREG_TCPWM0_GRP0_CNT19_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058099CUL)
#define CYREG_TCPWM0_GRP0_CNT19_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405809A0UL)
#define CYREG_TCPWM0_GRP0_CNT19_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405809A4UL)
#define CYREG_TCPWM0_GRP0_CNT19_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405809B0UL)
#define CYREG_TCPWM0_GRP0_CNT19_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405809C0UL)
#define CYREG_TCPWM0_GRP0_CNT19_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405809C4UL)
#define CYREG_TCPWM0_GRP0_CNT19_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405809C8UL)
#define CYREG_TCPWM0_GRP0_CNT19_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405809CCUL)
#define CYREG_TCPWM0_GRP0_CNT19_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405809D0UL)
#define CYREG_TCPWM0_GRP0_CNT19_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405809D4UL)
#define CYREG_TCPWM0_GRP0_CNT19_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405809F0UL)
#define CYREG_TCPWM0_GRP0_CNT19_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405809F4UL)
#define CYREG_TCPWM0_GRP0_CNT19_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405809F8UL)
#define CYREG_TCPWM0_GRP0_CNT19_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405809FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT20)
  */
#define CYREG_TCPWM0_GRP0_CNT20_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580A00UL)
#define CYREG_TCPWM0_GRP0_CNT20_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580A04UL)
#define CYREG_TCPWM0_GRP0_CNT20_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580A08UL)
#define CYREG_TCPWM0_GRP0_CNT20_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580A10UL)
#define CYREG_TCPWM0_GRP0_CNT20_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580A14UL)
#define CYREG_TCPWM0_GRP0_CNT20_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580A18UL)
#define CYREG_TCPWM0_GRP0_CNT20_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40580A1CUL)
#define CYREG_TCPWM0_GRP0_CNT20_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580A20UL)
#define CYREG_TCPWM0_GRP0_CNT20_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580A24UL)
#define CYREG_TCPWM0_GRP0_CNT20_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580A30UL)
#define CYREG_TCPWM0_GRP0_CNT20_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580A40UL)
#define CYREG_TCPWM0_GRP0_CNT20_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580A44UL)
#define CYREG_TCPWM0_GRP0_CNT20_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580A48UL)
#define CYREG_TCPWM0_GRP0_CNT20_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40580A4CUL)
#define CYREG_TCPWM0_GRP0_CNT20_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580A50UL)
#define CYREG_TCPWM0_GRP0_CNT20_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580A54UL)
#define CYREG_TCPWM0_GRP0_CNT20_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580A70UL)
#define CYREG_TCPWM0_GRP0_CNT20_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580A74UL)
#define CYREG_TCPWM0_GRP0_CNT20_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580A78UL)
#define CYREG_TCPWM0_GRP0_CNT20_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40580A7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT21)
  */
#define CYREG_TCPWM0_GRP0_CNT21_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580A80UL)
#define CYREG_TCPWM0_GRP0_CNT21_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580A84UL)
#define CYREG_TCPWM0_GRP0_CNT21_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580A88UL)
#define CYREG_TCPWM0_GRP0_CNT21_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580A90UL)
#define CYREG_TCPWM0_GRP0_CNT21_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580A94UL)
#define CYREG_TCPWM0_GRP0_CNT21_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580A98UL)
#define CYREG_TCPWM0_GRP0_CNT21_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40580A9CUL)
#define CYREG_TCPWM0_GRP0_CNT21_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580AA0UL)
#define CYREG_TCPWM0_GRP0_CNT21_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580AA4UL)
#define CYREG_TCPWM0_GRP0_CNT21_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580AB0UL)
#define CYREG_TCPWM0_GRP0_CNT21_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580AC0UL)
#define CYREG_TCPWM0_GRP0_CNT21_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580AC4UL)
#define CYREG_TCPWM0_GRP0_CNT21_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580AC8UL)
#define CYREG_TCPWM0_GRP0_CNT21_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40580ACCUL)
#define CYREG_TCPWM0_GRP0_CNT21_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580AD0UL)
#define CYREG_TCPWM0_GRP0_CNT21_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580AD4UL)
#define CYREG_TCPWM0_GRP0_CNT21_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580AF0UL)
#define CYREG_TCPWM0_GRP0_CNT21_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580AF4UL)
#define CYREG_TCPWM0_GRP0_CNT21_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580AF8UL)
#define CYREG_TCPWM0_GRP0_CNT21_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40580AFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT22)
  */
#define CYREG_TCPWM0_GRP0_CNT22_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580B00UL)
#define CYREG_TCPWM0_GRP0_CNT22_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580B04UL)
#define CYREG_TCPWM0_GRP0_CNT22_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580B08UL)
#define CYREG_TCPWM0_GRP0_CNT22_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580B10UL)
#define CYREG_TCPWM0_GRP0_CNT22_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580B14UL)
#define CYREG_TCPWM0_GRP0_CNT22_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580B18UL)
#define CYREG_TCPWM0_GRP0_CNT22_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40580B1CUL)
#define CYREG_TCPWM0_GRP0_CNT22_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580B20UL)
#define CYREG_TCPWM0_GRP0_CNT22_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580B24UL)
#define CYREG_TCPWM0_GRP0_CNT22_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580B30UL)
#define CYREG_TCPWM0_GRP0_CNT22_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580B40UL)
#define CYREG_TCPWM0_GRP0_CNT22_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580B44UL)
#define CYREG_TCPWM0_GRP0_CNT22_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580B48UL)
#define CYREG_TCPWM0_GRP0_CNT22_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40580B4CUL)
#define CYREG_TCPWM0_GRP0_CNT22_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580B50UL)
#define CYREG_TCPWM0_GRP0_CNT22_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580B54UL)
#define CYREG_TCPWM0_GRP0_CNT22_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580B70UL)
#define CYREG_TCPWM0_GRP0_CNT22_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580B74UL)
#define CYREG_TCPWM0_GRP0_CNT22_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580B78UL)
#define CYREG_TCPWM0_GRP0_CNT22_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40580B7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT23)
  */
#define CYREG_TCPWM0_GRP0_CNT23_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580B80UL)
#define CYREG_TCPWM0_GRP0_CNT23_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580B84UL)
#define CYREG_TCPWM0_GRP0_CNT23_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580B88UL)
#define CYREG_TCPWM0_GRP0_CNT23_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580B90UL)
#define CYREG_TCPWM0_GRP0_CNT23_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580B94UL)
#define CYREG_TCPWM0_GRP0_CNT23_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580B98UL)
#define CYREG_TCPWM0_GRP0_CNT23_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40580B9CUL)
#define CYREG_TCPWM0_GRP0_CNT23_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580BA0UL)
#define CYREG_TCPWM0_GRP0_CNT23_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580BA4UL)
#define CYREG_TCPWM0_GRP0_CNT23_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580BB0UL)
#define CYREG_TCPWM0_GRP0_CNT23_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580BC0UL)
#define CYREG_TCPWM0_GRP0_CNT23_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580BC4UL)
#define CYREG_TCPWM0_GRP0_CNT23_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580BC8UL)
#define CYREG_TCPWM0_GRP0_CNT23_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40580BCCUL)
#define CYREG_TCPWM0_GRP0_CNT23_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580BD0UL)
#define CYREG_TCPWM0_GRP0_CNT23_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580BD4UL)
#define CYREG_TCPWM0_GRP0_CNT23_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580BF0UL)
#define CYREG_TCPWM0_GRP0_CNT23_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580BF4UL)
#define CYREG_TCPWM0_GRP0_CNT23_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580BF8UL)
#define CYREG_TCPWM0_GRP0_CNT23_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40580BFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT24)
  */
#define CYREG_TCPWM0_GRP0_CNT24_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580C00UL)
#define CYREG_TCPWM0_GRP0_CNT24_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580C04UL)
#define CYREG_TCPWM0_GRP0_CNT24_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580C08UL)
#define CYREG_TCPWM0_GRP0_CNT24_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580C10UL)
#define CYREG_TCPWM0_GRP0_CNT24_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580C14UL)
#define CYREG_TCPWM0_GRP0_CNT24_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580C18UL)
#define CYREG_TCPWM0_GRP0_CNT24_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40580C1CUL)
#define CYREG_TCPWM0_GRP0_CNT24_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580C20UL)
#define CYREG_TCPWM0_GRP0_CNT24_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580C24UL)
#define CYREG_TCPWM0_GRP0_CNT24_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580C30UL)
#define CYREG_TCPWM0_GRP0_CNT24_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580C40UL)
#define CYREG_TCPWM0_GRP0_CNT24_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580C44UL)
#define CYREG_TCPWM0_GRP0_CNT24_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580C48UL)
#define CYREG_TCPWM0_GRP0_CNT24_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40580C4CUL)
#define CYREG_TCPWM0_GRP0_CNT24_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580C50UL)
#define CYREG_TCPWM0_GRP0_CNT24_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580C54UL)
#define CYREG_TCPWM0_GRP0_CNT24_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580C70UL)
#define CYREG_TCPWM0_GRP0_CNT24_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580C74UL)
#define CYREG_TCPWM0_GRP0_CNT24_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580C78UL)
#define CYREG_TCPWM0_GRP0_CNT24_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40580C7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT25)
  */
#define CYREG_TCPWM0_GRP0_CNT25_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580C80UL)
#define CYREG_TCPWM0_GRP0_CNT25_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580C84UL)
#define CYREG_TCPWM0_GRP0_CNT25_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580C88UL)
#define CYREG_TCPWM0_GRP0_CNT25_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580C90UL)
#define CYREG_TCPWM0_GRP0_CNT25_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580C94UL)
#define CYREG_TCPWM0_GRP0_CNT25_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580C98UL)
#define CYREG_TCPWM0_GRP0_CNT25_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40580C9CUL)
#define CYREG_TCPWM0_GRP0_CNT25_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580CA0UL)
#define CYREG_TCPWM0_GRP0_CNT25_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580CA4UL)
#define CYREG_TCPWM0_GRP0_CNT25_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580CB0UL)
#define CYREG_TCPWM0_GRP0_CNT25_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580CC0UL)
#define CYREG_TCPWM0_GRP0_CNT25_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580CC4UL)
#define CYREG_TCPWM0_GRP0_CNT25_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580CC8UL)
#define CYREG_TCPWM0_GRP0_CNT25_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40580CCCUL)
#define CYREG_TCPWM0_GRP0_CNT25_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580CD0UL)
#define CYREG_TCPWM0_GRP0_CNT25_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580CD4UL)
#define CYREG_TCPWM0_GRP0_CNT25_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580CF0UL)
#define CYREG_TCPWM0_GRP0_CNT25_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580CF4UL)
#define CYREG_TCPWM0_GRP0_CNT25_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580CF8UL)
#define CYREG_TCPWM0_GRP0_CNT25_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40580CFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT26)
  */
#define CYREG_TCPWM0_GRP0_CNT26_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580D00UL)
#define CYREG_TCPWM0_GRP0_CNT26_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580D04UL)
#define CYREG_TCPWM0_GRP0_CNT26_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580D08UL)
#define CYREG_TCPWM0_GRP0_CNT26_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580D10UL)
#define CYREG_TCPWM0_GRP0_CNT26_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580D14UL)
#define CYREG_TCPWM0_GRP0_CNT26_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580D18UL)
#define CYREG_TCPWM0_GRP0_CNT26_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40580D1CUL)
#define CYREG_TCPWM0_GRP0_CNT26_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580D20UL)
#define CYREG_TCPWM0_GRP0_CNT26_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580D24UL)
#define CYREG_TCPWM0_GRP0_CNT26_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580D30UL)
#define CYREG_TCPWM0_GRP0_CNT26_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580D40UL)
#define CYREG_TCPWM0_GRP0_CNT26_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580D44UL)
#define CYREG_TCPWM0_GRP0_CNT26_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580D48UL)
#define CYREG_TCPWM0_GRP0_CNT26_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40580D4CUL)
#define CYREG_TCPWM0_GRP0_CNT26_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580D50UL)
#define CYREG_TCPWM0_GRP0_CNT26_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580D54UL)
#define CYREG_TCPWM0_GRP0_CNT26_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580D70UL)
#define CYREG_TCPWM0_GRP0_CNT26_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580D74UL)
#define CYREG_TCPWM0_GRP0_CNT26_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580D78UL)
#define CYREG_TCPWM0_GRP0_CNT26_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40580D7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT27)
  */
#define CYREG_TCPWM0_GRP0_CNT27_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580D80UL)
#define CYREG_TCPWM0_GRP0_CNT27_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580D84UL)
#define CYREG_TCPWM0_GRP0_CNT27_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580D88UL)
#define CYREG_TCPWM0_GRP0_CNT27_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580D90UL)
#define CYREG_TCPWM0_GRP0_CNT27_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580D94UL)
#define CYREG_TCPWM0_GRP0_CNT27_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580D98UL)
#define CYREG_TCPWM0_GRP0_CNT27_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40580D9CUL)
#define CYREG_TCPWM0_GRP0_CNT27_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580DA0UL)
#define CYREG_TCPWM0_GRP0_CNT27_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580DA4UL)
#define CYREG_TCPWM0_GRP0_CNT27_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580DB0UL)
#define CYREG_TCPWM0_GRP0_CNT27_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580DC0UL)
#define CYREG_TCPWM0_GRP0_CNT27_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580DC4UL)
#define CYREG_TCPWM0_GRP0_CNT27_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580DC8UL)
#define CYREG_TCPWM0_GRP0_CNT27_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40580DCCUL)
#define CYREG_TCPWM0_GRP0_CNT27_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580DD0UL)
#define CYREG_TCPWM0_GRP0_CNT27_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580DD4UL)
#define CYREG_TCPWM0_GRP0_CNT27_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580DF0UL)
#define CYREG_TCPWM0_GRP0_CNT27_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580DF4UL)
#define CYREG_TCPWM0_GRP0_CNT27_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580DF8UL)
#define CYREG_TCPWM0_GRP0_CNT27_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40580DFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT28)
  */
#define CYREG_TCPWM0_GRP0_CNT28_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580E00UL)
#define CYREG_TCPWM0_GRP0_CNT28_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580E04UL)
#define CYREG_TCPWM0_GRP0_CNT28_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580E08UL)
#define CYREG_TCPWM0_GRP0_CNT28_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580E10UL)
#define CYREG_TCPWM0_GRP0_CNT28_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580E14UL)
#define CYREG_TCPWM0_GRP0_CNT28_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580E18UL)
#define CYREG_TCPWM0_GRP0_CNT28_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40580E1CUL)
#define CYREG_TCPWM0_GRP0_CNT28_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580E20UL)
#define CYREG_TCPWM0_GRP0_CNT28_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580E24UL)
#define CYREG_TCPWM0_GRP0_CNT28_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580E30UL)
#define CYREG_TCPWM0_GRP0_CNT28_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580E40UL)
#define CYREG_TCPWM0_GRP0_CNT28_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580E44UL)
#define CYREG_TCPWM0_GRP0_CNT28_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580E48UL)
#define CYREG_TCPWM0_GRP0_CNT28_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40580E4CUL)
#define CYREG_TCPWM0_GRP0_CNT28_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580E50UL)
#define CYREG_TCPWM0_GRP0_CNT28_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580E54UL)
#define CYREG_TCPWM0_GRP0_CNT28_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580E70UL)
#define CYREG_TCPWM0_GRP0_CNT28_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580E74UL)
#define CYREG_TCPWM0_GRP0_CNT28_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580E78UL)
#define CYREG_TCPWM0_GRP0_CNT28_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40580E7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT29)
  */
#define CYREG_TCPWM0_GRP0_CNT29_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580E80UL)
#define CYREG_TCPWM0_GRP0_CNT29_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580E84UL)
#define CYREG_TCPWM0_GRP0_CNT29_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580E88UL)
#define CYREG_TCPWM0_GRP0_CNT29_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580E90UL)
#define CYREG_TCPWM0_GRP0_CNT29_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580E94UL)
#define CYREG_TCPWM0_GRP0_CNT29_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580E98UL)
#define CYREG_TCPWM0_GRP0_CNT29_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40580E9CUL)
#define CYREG_TCPWM0_GRP0_CNT29_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580EA0UL)
#define CYREG_TCPWM0_GRP0_CNT29_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580EA4UL)
#define CYREG_TCPWM0_GRP0_CNT29_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580EB0UL)
#define CYREG_TCPWM0_GRP0_CNT29_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580EC0UL)
#define CYREG_TCPWM0_GRP0_CNT29_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580EC4UL)
#define CYREG_TCPWM0_GRP0_CNT29_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580EC8UL)
#define CYREG_TCPWM0_GRP0_CNT29_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40580ECCUL)
#define CYREG_TCPWM0_GRP0_CNT29_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580ED0UL)
#define CYREG_TCPWM0_GRP0_CNT29_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580ED4UL)
#define CYREG_TCPWM0_GRP0_CNT29_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580EF0UL)
#define CYREG_TCPWM0_GRP0_CNT29_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580EF4UL)
#define CYREG_TCPWM0_GRP0_CNT29_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580EF8UL)
#define CYREG_TCPWM0_GRP0_CNT29_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40580EFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT30)
  */
#define CYREG_TCPWM0_GRP0_CNT30_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580F00UL)
#define CYREG_TCPWM0_GRP0_CNT30_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580F04UL)
#define CYREG_TCPWM0_GRP0_CNT30_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580F08UL)
#define CYREG_TCPWM0_GRP0_CNT30_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580F10UL)
#define CYREG_TCPWM0_GRP0_CNT30_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580F14UL)
#define CYREG_TCPWM0_GRP0_CNT30_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580F18UL)
#define CYREG_TCPWM0_GRP0_CNT30_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40580F1CUL)
#define CYREG_TCPWM0_GRP0_CNT30_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580F20UL)
#define CYREG_TCPWM0_GRP0_CNT30_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580F24UL)
#define CYREG_TCPWM0_GRP0_CNT30_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580F30UL)
#define CYREG_TCPWM0_GRP0_CNT30_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580F40UL)
#define CYREG_TCPWM0_GRP0_CNT30_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580F44UL)
#define CYREG_TCPWM0_GRP0_CNT30_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580F48UL)
#define CYREG_TCPWM0_GRP0_CNT30_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40580F4CUL)
#define CYREG_TCPWM0_GRP0_CNT30_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580F50UL)
#define CYREG_TCPWM0_GRP0_CNT30_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580F54UL)
#define CYREG_TCPWM0_GRP0_CNT30_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580F70UL)
#define CYREG_TCPWM0_GRP0_CNT30_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580F74UL)
#define CYREG_TCPWM0_GRP0_CNT30_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580F78UL)
#define CYREG_TCPWM0_GRP0_CNT30_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40580F7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT31)
  */
#define CYREG_TCPWM0_GRP0_CNT31_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40580F80UL)
#define CYREG_TCPWM0_GRP0_CNT31_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40580F84UL)
#define CYREG_TCPWM0_GRP0_CNT31_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40580F88UL)
#define CYREG_TCPWM0_GRP0_CNT31_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40580F90UL)
#define CYREG_TCPWM0_GRP0_CNT31_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40580F94UL)
#define CYREG_TCPWM0_GRP0_CNT31_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40580F98UL)
#define CYREG_TCPWM0_GRP0_CNT31_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40580F9CUL)
#define CYREG_TCPWM0_GRP0_CNT31_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40580FA0UL)
#define CYREG_TCPWM0_GRP0_CNT31_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40580FA4UL)
#define CYREG_TCPWM0_GRP0_CNT31_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40580FB0UL)
#define CYREG_TCPWM0_GRP0_CNT31_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40580FC0UL)
#define CYREG_TCPWM0_GRP0_CNT31_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40580FC4UL)
#define CYREG_TCPWM0_GRP0_CNT31_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40580FC8UL)
#define CYREG_TCPWM0_GRP0_CNT31_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40580FCCUL)
#define CYREG_TCPWM0_GRP0_CNT31_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40580FD0UL)
#define CYREG_TCPWM0_GRP0_CNT31_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40580FD4UL)
#define CYREG_TCPWM0_GRP0_CNT31_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40580FF0UL)
#define CYREG_TCPWM0_GRP0_CNT31_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40580FF4UL)
#define CYREG_TCPWM0_GRP0_CNT31_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40580FF8UL)
#define CYREG_TCPWM0_GRP0_CNT31_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40580FFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT32)
  */
#define CYREG_TCPWM0_GRP0_CNT32_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581000UL)
#define CYREG_TCPWM0_GRP0_CNT32_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581004UL)
#define CYREG_TCPWM0_GRP0_CNT32_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581008UL)
#define CYREG_TCPWM0_GRP0_CNT32_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581010UL)
#define CYREG_TCPWM0_GRP0_CNT32_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581014UL)
#define CYREG_TCPWM0_GRP0_CNT32_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581018UL)
#define CYREG_TCPWM0_GRP0_CNT32_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058101CUL)
#define CYREG_TCPWM0_GRP0_CNT32_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581020UL)
#define CYREG_TCPWM0_GRP0_CNT32_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581024UL)
#define CYREG_TCPWM0_GRP0_CNT32_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581030UL)
#define CYREG_TCPWM0_GRP0_CNT32_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581040UL)
#define CYREG_TCPWM0_GRP0_CNT32_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581044UL)
#define CYREG_TCPWM0_GRP0_CNT32_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581048UL)
#define CYREG_TCPWM0_GRP0_CNT32_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058104CUL)
#define CYREG_TCPWM0_GRP0_CNT32_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581050UL)
#define CYREG_TCPWM0_GRP0_CNT32_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581054UL)
#define CYREG_TCPWM0_GRP0_CNT32_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581070UL)
#define CYREG_TCPWM0_GRP0_CNT32_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581074UL)
#define CYREG_TCPWM0_GRP0_CNT32_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581078UL)
#define CYREG_TCPWM0_GRP0_CNT32_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058107CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT33)
  */
#define CYREG_TCPWM0_GRP0_CNT33_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581080UL)
#define CYREG_TCPWM0_GRP0_CNT33_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581084UL)
#define CYREG_TCPWM0_GRP0_CNT33_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581088UL)
#define CYREG_TCPWM0_GRP0_CNT33_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581090UL)
#define CYREG_TCPWM0_GRP0_CNT33_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581094UL)
#define CYREG_TCPWM0_GRP0_CNT33_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581098UL)
#define CYREG_TCPWM0_GRP0_CNT33_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058109CUL)
#define CYREG_TCPWM0_GRP0_CNT33_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405810A0UL)
#define CYREG_TCPWM0_GRP0_CNT33_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405810A4UL)
#define CYREG_TCPWM0_GRP0_CNT33_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405810B0UL)
#define CYREG_TCPWM0_GRP0_CNT33_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405810C0UL)
#define CYREG_TCPWM0_GRP0_CNT33_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405810C4UL)
#define CYREG_TCPWM0_GRP0_CNT33_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405810C8UL)
#define CYREG_TCPWM0_GRP0_CNT33_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405810CCUL)
#define CYREG_TCPWM0_GRP0_CNT33_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405810D0UL)
#define CYREG_TCPWM0_GRP0_CNT33_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405810D4UL)
#define CYREG_TCPWM0_GRP0_CNT33_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405810F0UL)
#define CYREG_TCPWM0_GRP0_CNT33_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405810F4UL)
#define CYREG_TCPWM0_GRP0_CNT33_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405810F8UL)
#define CYREG_TCPWM0_GRP0_CNT33_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405810FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT34)
  */
#define CYREG_TCPWM0_GRP0_CNT34_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581100UL)
#define CYREG_TCPWM0_GRP0_CNT34_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581104UL)
#define CYREG_TCPWM0_GRP0_CNT34_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581108UL)
#define CYREG_TCPWM0_GRP0_CNT34_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581110UL)
#define CYREG_TCPWM0_GRP0_CNT34_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581114UL)
#define CYREG_TCPWM0_GRP0_CNT34_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581118UL)
#define CYREG_TCPWM0_GRP0_CNT34_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058111CUL)
#define CYREG_TCPWM0_GRP0_CNT34_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581120UL)
#define CYREG_TCPWM0_GRP0_CNT34_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581124UL)
#define CYREG_TCPWM0_GRP0_CNT34_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581130UL)
#define CYREG_TCPWM0_GRP0_CNT34_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581140UL)
#define CYREG_TCPWM0_GRP0_CNT34_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581144UL)
#define CYREG_TCPWM0_GRP0_CNT34_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581148UL)
#define CYREG_TCPWM0_GRP0_CNT34_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058114CUL)
#define CYREG_TCPWM0_GRP0_CNT34_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581150UL)
#define CYREG_TCPWM0_GRP0_CNT34_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581154UL)
#define CYREG_TCPWM0_GRP0_CNT34_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581170UL)
#define CYREG_TCPWM0_GRP0_CNT34_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581174UL)
#define CYREG_TCPWM0_GRP0_CNT34_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581178UL)
#define CYREG_TCPWM0_GRP0_CNT34_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058117CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT35)
  */
#define CYREG_TCPWM0_GRP0_CNT35_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581180UL)
#define CYREG_TCPWM0_GRP0_CNT35_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581184UL)
#define CYREG_TCPWM0_GRP0_CNT35_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581188UL)
#define CYREG_TCPWM0_GRP0_CNT35_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581190UL)
#define CYREG_TCPWM0_GRP0_CNT35_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581194UL)
#define CYREG_TCPWM0_GRP0_CNT35_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581198UL)
#define CYREG_TCPWM0_GRP0_CNT35_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058119CUL)
#define CYREG_TCPWM0_GRP0_CNT35_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405811A0UL)
#define CYREG_TCPWM0_GRP0_CNT35_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405811A4UL)
#define CYREG_TCPWM0_GRP0_CNT35_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405811B0UL)
#define CYREG_TCPWM0_GRP0_CNT35_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405811C0UL)
#define CYREG_TCPWM0_GRP0_CNT35_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405811C4UL)
#define CYREG_TCPWM0_GRP0_CNT35_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405811C8UL)
#define CYREG_TCPWM0_GRP0_CNT35_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405811CCUL)
#define CYREG_TCPWM0_GRP0_CNT35_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405811D0UL)
#define CYREG_TCPWM0_GRP0_CNT35_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405811D4UL)
#define CYREG_TCPWM0_GRP0_CNT35_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405811F0UL)
#define CYREG_TCPWM0_GRP0_CNT35_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405811F4UL)
#define CYREG_TCPWM0_GRP0_CNT35_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405811F8UL)
#define CYREG_TCPWM0_GRP0_CNT35_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405811FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT36)
  */
#define CYREG_TCPWM0_GRP0_CNT36_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581200UL)
#define CYREG_TCPWM0_GRP0_CNT36_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581204UL)
#define CYREG_TCPWM0_GRP0_CNT36_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581208UL)
#define CYREG_TCPWM0_GRP0_CNT36_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581210UL)
#define CYREG_TCPWM0_GRP0_CNT36_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581214UL)
#define CYREG_TCPWM0_GRP0_CNT36_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581218UL)
#define CYREG_TCPWM0_GRP0_CNT36_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058121CUL)
#define CYREG_TCPWM0_GRP0_CNT36_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581220UL)
#define CYREG_TCPWM0_GRP0_CNT36_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581224UL)
#define CYREG_TCPWM0_GRP0_CNT36_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581230UL)
#define CYREG_TCPWM0_GRP0_CNT36_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581240UL)
#define CYREG_TCPWM0_GRP0_CNT36_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581244UL)
#define CYREG_TCPWM0_GRP0_CNT36_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581248UL)
#define CYREG_TCPWM0_GRP0_CNT36_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058124CUL)
#define CYREG_TCPWM0_GRP0_CNT36_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581250UL)
#define CYREG_TCPWM0_GRP0_CNT36_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581254UL)
#define CYREG_TCPWM0_GRP0_CNT36_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581270UL)
#define CYREG_TCPWM0_GRP0_CNT36_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581274UL)
#define CYREG_TCPWM0_GRP0_CNT36_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581278UL)
#define CYREG_TCPWM0_GRP0_CNT36_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058127CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT37)
  */
#define CYREG_TCPWM0_GRP0_CNT37_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581280UL)
#define CYREG_TCPWM0_GRP0_CNT37_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581284UL)
#define CYREG_TCPWM0_GRP0_CNT37_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581288UL)
#define CYREG_TCPWM0_GRP0_CNT37_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581290UL)
#define CYREG_TCPWM0_GRP0_CNT37_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581294UL)
#define CYREG_TCPWM0_GRP0_CNT37_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581298UL)
#define CYREG_TCPWM0_GRP0_CNT37_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058129CUL)
#define CYREG_TCPWM0_GRP0_CNT37_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405812A0UL)
#define CYREG_TCPWM0_GRP0_CNT37_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405812A4UL)
#define CYREG_TCPWM0_GRP0_CNT37_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405812B0UL)
#define CYREG_TCPWM0_GRP0_CNT37_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405812C0UL)
#define CYREG_TCPWM0_GRP0_CNT37_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405812C4UL)
#define CYREG_TCPWM0_GRP0_CNT37_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405812C8UL)
#define CYREG_TCPWM0_GRP0_CNT37_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405812CCUL)
#define CYREG_TCPWM0_GRP0_CNT37_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405812D0UL)
#define CYREG_TCPWM0_GRP0_CNT37_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405812D4UL)
#define CYREG_TCPWM0_GRP0_CNT37_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405812F0UL)
#define CYREG_TCPWM0_GRP0_CNT37_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405812F4UL)
#define CYREG_TCPWM0_GRP0_CNT37_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405812F8UL)
#define CYREG_TCPWM0_GRP0_CNT37_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405812FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT38)
  */
#define CYREG_TCPWM0_GRP0_CNT38_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581300UL)
#define CYREG_TCPWM0_GRP0_CNT38_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581304UL)
#define CYREG_TCPWM0_GRP0_CNT38_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581308UL)
#define CYREG_TCPWM0_GRP0_CNT38_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581310UL)
#define CYREG_TCPWM0_GRP0_CNT38_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581314UL)
#define CYREG_TCPWM0_GRP0_CNT38_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581318UL)
#define CYREG_TCPWM0_GRP0_CNT38_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058131CUL)
#define CYREG_TCPWM0_GRP0_CNT38_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581320UL)
#define CYREG_TCPWM0_GRP0_CNT38_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581324UL)
#define CYREG_TCPWM0_GRP0_CNT38_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581330UL)
#define CYREG_TCPWM0_GRP0_CNT38_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581340UL)
#define CYREG_TCPWM0_GRP0_CNT38_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581344UL)
#define CYREG_TCPWM0_GRP0_CNT38_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581348UL)
#define CYREG_TCPWM0_GRP0_CNT38_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058134CUL)
#define CYREG_TCPWM0_GRP0_CNT38_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581350UL)
#define CYREG_TCPWM0_GRP0_CNT38_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581354UL)
#define CYREG_TCPWM0_GRP0_CNT38_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581370UL)
#define CYREG_TCPWM0_GRP0_CNT38_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581374UL)
#define CYREG_TCPWM0_GRP0_CNT38_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581378UL)
#define CYREG_TCPWM0_GRP0_CNT38_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058137CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT39)
  */
#define CYREG_TCPWM0_GRP0_CNT39_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581380UL)
#define CYREG_TCPWM0_GRP0_CNT39_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581384UL)
#define CYREG_TCPWM0_GRP0_CNT39_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581388UL)
#define CYREG_TCPWM0_GRP0_CNT39_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581390UL)
#define CYREG_TCPWM0_GRP0_CNT39_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581394UL)
#define CYREG_TCPWM0_GRP0_CNT39_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581398UL)
#define CYREG_TCPWM0_GRP0_CNT39_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058139CUL)
#define CYREG_TCPWM0_GRP0_CNT39_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405813A0UL)
#define CYREG_TCPWM0_GRP0_CNT39_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405813A4UL)
#define CYREG_TCPWM0_GRP0_CNT39_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405813B0UL)
#define CYREG_TCPWM0_GRP0_CNT39_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405813C0UL)
#define CYREG_TCPWM0_GRP0_CNT39_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405813C4UL)
#define CYREG_TCPWM0_GRP0_CNT39_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405813C8UL)
#define CYREG_TCPWM0_GRP0_CNT39_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405813CCUL)
#define CYREG_TCPWM0_GRP0_CNT39_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405813D0UL)
#define CYREG_TCPWM0_GRP0_CNT39_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405813D4UL)
#define CYREG_TCPWM0_GRP0_CNT39_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405813F0UL)
#define CYREG_TCPWM0_GRP0_CNT39_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405813F4UL)
#define CYREG_TCPWM0_GRP0_CNT39_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405813F8UL)
#define CYREG_TCPWM0_GRP0_CNT39_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405813FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT40)
  */
#define CYREG_TCPWM0_GRP0_CNT40_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581400UL)
#define CYREG_TCPWM0_GRP0_CNT40_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581404UL)
#define CYREG_TCPWM0_GRP0_CNT40_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581408UL)
#define CYREG_TCPWM0_GRP0_CNT40_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581410UL)
#define CYREG_TCPWM0_GRP0_CNT40_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581414UL)
#define CYREG_TCPWM0_GRP0_CNT40_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581418UL)
#define CYREG_TCPWM0_GRP0_CNT40_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058141CUL)
#define CYREG_TCPWM0_GRP0_CNT40_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581420UL)
#define CYREG_TCPWM0_GRP0_CNT40_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581424UL)
#define CYREG_TCPWM0_GRP0_CNT40_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581430UL)
#define CYREG_TCPWM0_GRP0_CNT40_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581440UL)
#define CYREG_TCPWM0_GRP0_CNT40_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581444UL)
#define CYREG_TCPWM0_GRP0_CNT40_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581448UL)
#define CYREG_TCPWM0_GRP0_CNT40_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058144CUL)
#define CYREG_TCPWM0_GRP0_CNT40_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581450UL)
#define CYREG_TCPWM0_GRP0_CNT40_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581454UL)
#define CYREG_TCPWM0_GRP0_CNT40_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581470UL)
#define CYREG_TCPWM0_GRP0_CNT40_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581474UL)
#define CYREG_TCPWM0_GRP0_CNT40_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581478UL)
#define CYREG_TCPWM0_GRP0_CNT40_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058147CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT41)
  */
#define CYREG_TCPWM0_GRP0_CNT41_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581480UL)
#define CYREG_TCPWM0_GRP0_CNT41_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581484UL)
#define CYREG_TCPWM0_GRP0_CNT41_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581488UL)
#define CYREG_TCPWM0_GRP0_CNT41_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581490UL)
#define CYREG_TCPWM0_GRP0_CNT41_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581494UL)
#define CYREG_TCPWM0_GRP0_CNT41_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581498UL)
#define CYREG_TCPWM0_GRP0_CNT41_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058149CUL)
#define CYREG_TCPWM0_GRP0_CNT41_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405814A0UL)
#define CYREG_TCPWM0_GRP0_CNT41_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405814A4UL)
#define CYREG_TCPWM0_GRP0_CNT41_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405814B0UL)
#define CYREG_TCPWM0_GRP0_CNT41_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405814C0UL)
#define CYREG_TCPWM0_GRP0_CNT41_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405814C4UL)
#define CYREG_TCPWM0_GRP0_CNT41_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405814C8UL)
#define CYREG_TCPWM0_GRP0_CNT41_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405814CCUL)
#define CYREG_TCPWM0_GRP0_CNT41_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405814D0UL)
#define CYREG_TCPWM0_GRP0_CNT41_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405814D4UL)
#define CYREG_TCPWM0_GRP0_CNT41_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405814F0UL)
#define CYREG_TCPWM0_GRP0_CNT41_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405814F4UL)
#define CYREG_TCPWM0_GRP0_CNT41_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405814F8UL)
#define CYREG_TCPWM0_GRP0_CNT41_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405814FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT42)
  */
#define CYREG_TCPWM0_GRP0_CNT42_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581500UL)
#define CYREG_TCPWM0_GRP0_CNT42_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581504UL)
#define CYREG_TCPWM0_GRP0_CNT42_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581508UL)
#define CYREG_TCPWM0_GRP0_CNT42_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581510UL)
#define CYREG_TCPWM0_GRP0_CNT42_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581514UL)
#define CYREG_TCPWM0_GRP0_CNT42_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581518UL)
#define CYREG_TCPWM0_GRP0_CNT42_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058151CUL)
#define CYREG_TCPWM0_GRP0_CNT42_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581520UL)
#define CYREG_TCPWM0_GRP0_CNT42_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581524UL)
#define CYREG_TCPWM0_GRP0_CNT42_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581530UL)
#define CYREG_TCPWM0_GRP0_CNT42_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581540UL)
#define CYREG_TCPWM0_GRP0_CNT42_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581544UL)
#define CYREG_TCPWM0_GRP0_CNT42_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581548UL)
#define CYREG_TCPWM0_GRP0_CNT42_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058154CUL)
#define CYREG_TCPWM0_GRP0_CNT42_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581550UL)
#define CYREG_TCPWM0_GRP0_CNT42_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581554UL)
#define CYREG_TCPWM0_GRP0_CNT42_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581570UL)
#define CYREG_TCPWM0_GRP0_CNT42_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581574UL)
#define CYREG_TCPWM0_GRP0_CNT42_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581578UL)
#define CYREG_TCPWM0_GRP0_CNT42_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058157CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT43)
  */
#define CYREG_TCPWM0_GRP0_CNT43_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581580UL)
#define CYREG_TCPWM0_GRP0_CNT43_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581584UL)
#define CYREG_TCPWM0_GRP0_CNT43_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581588UL)
#define CYREG_TCPWM0_GRP0_CNT43_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581590UL)
#define CYREG_TCPWM0_GRP0_CNT43_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581594UL)
#define CYREG_TCPWM0_GRP0_CNT43_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581598UL)
#define CYREG_TCPWM0_GRP0_CNT43_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058159CUL)
#define CYREG_TCPWM0_GRP0_CNT43_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405815A0UL)
#define CYREG_TCPWM0_GRP0_CNT43_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405815A4UL)
#define CYREG_TCPWM0_GRP0_CNT43_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405815B0UL)
#define CYREG_TCPWM0_GRP0_CNT43_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405815C0UL)
#define CYREG_TCPWM0_GRP0_CNT43_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405815C4UL)
#define CYREG_TCPWM0_GRP0_CNT43_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405815C8UL)
#define CYREG_TCPWM0_GRP0_CNT43_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405815CCUL)
#define CYREG_TCPWM0_GRP0_CNT43_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405815D0UL)
#define CYREG_TCPWM0_GRP0_CNT43_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405815D4UL)
#define CYREG_TCPWM0_GRP0_CNT43_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405815F0UL)
#define CYREG_TCPWM0_GRP0_CNT43_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405815F4UL)
#define CYREG_TCPWM0_GRP0_CNT43_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405815F8UL)
#define CYREG_TCPWM0_GRP0_CNT43_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405815FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT44)
  */
#define CYREG_TCPWM0_GRP0_CNT44_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581600UL)
#define CYREG_TCPWM0_GRP0_CNT44_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581604UL)
#define CYREG_TCPWM0_GRP0_CNT44_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581608UL)
#define CYREG_TCPWM0_GRP0_CNT44_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581610UL)
#define CYREG_TCPWM0_GRP0_CNT44_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581614UL)
#define CYREG_TCPWM0_GRP0_CNT44_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581618UL)
#define CYREG_TCPWM0_GRP0_CNT44_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058161CUL)
#define CYREG_TCPWM0_GRP0_CNT44_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581620UL)
#define CYREG_TCPWM0_GRP0_CNT44_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581624UL)
#define CYREG_TCPWM0_GRP0_CNT44_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581630UL)
#define CYREG_TCPWM0_GRP0_CNT44_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581640UL)
#define CYREG_TCPWM0_GRP0_CNT44_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581644UL)
#define CYREG_TCPWM0_GRP0_CNT44_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581648UL)
#define CYREG_TCPWM0_GRP0_CNT44_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058164CUL)
#define CYREG_TCPWM0_GRP0_CNT44_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581650UL)
#define CYREG_TCPWM0_GRP0_CNT44_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581654UL)
#define CYREG_TCPWM0_GRP0_CNT44_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581670UL)
#define CYREG_TCPWM0_GRP0_CNT44_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581674UL)
#define CYREG_TCPWM0_GRP0_CNT44_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581678UL)
#define CYREG_TCPWM0_GRP0_CNT44_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058167CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT45)
  */
#define CYREG_TCPWM0_GRP0_CNT45_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581680UL)
#define CYREG_TCPWM0_GRP0_CNT45_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581684UL)
#define CYREG_TCPWM0_GRP0_CNT45_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581688UL)
#define CYREG_TCPWM0_GRP0_CNT45_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581690UL)
#define CYREG_TCPWM0_GRP0_CNT45_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581694UL)
#define CYREG_TCPWM0_GRP0_CNT45_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581698UL)
#define CYREG_TCPWM0_GRP0_CNT45_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058169CUL)
#define CYREG_TCPWM0_GRP0_CNT45_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405816A0UL)
#define CYREG_TCPWM0_GRP0_CNT45_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405816A4UL)
#define CYREG_TCPWM0_GRP0_CNT45_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405816B0UL)
#define CYREG_TCPWM0_GRP0_CNT45_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405816C0UL)
#define CYREG_TCPWM0_GRP0_CNT45_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405816C4UL)
#define CYREG_TCPWM0_GRP0_CNT45_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405816C8UL)
#define CYREG_TCPWM0_GRP0_CNT45_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405816CCUL)
#define CYREG_TCPWM0_GRP0_CNT45_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405816D0UL)
#define CYREG_TCPWM0_GRP0_CNT45_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405816D4UL)
#define CYREG_TCPWM0_GRP0_CNT45_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405816F0UL)
#define CYREG_TCPWM0_GRP0_CNT45_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405816F4UL)
#define CYREG_TCPWM0_GRP0_CNT45_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405816F8UL)
#define CYREG_TCPWM0_GRP0_CNT45_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405816FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT46)
  */
#define CYREG_TCPWM0_GRP0_CNT46_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581700UL)
#define CYREG_TCPWM0_GRP0_CNT46_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581704UL)
#define CYREG_TCPWM0_GRP0_CNT46_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581708UL)
#define CYREG_TCPWM0_GRP0_CNT46_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581710UL)
#define CYREG_TCPWM0_GRP0_CNT46_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581714UL)
#define CYREG_TCPWM0_GRP0_CNT46_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581718UL)
#define CYREG_TCPWM0_GRP0_CNT46_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058171CUL)
#define CYREG_TCPWM0_GRP0_CNT46_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581720UL)
#define CYREG_TCPWM0_GRP0_CNT46_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581724UL)
#define CYREG_TCPWM0_GRP0_CNT46_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581730UL)
#define CYREG_TCPWM0_GRP0_CNT46_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581740UL)
#define CYREG_TCPWM0_GRP0_CNT46_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581744UL)
#define CYREG_TCPWM0_GRP0_CNT46_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581748UL)
#define CYREG_TCPWM0_GRP0_CNT46_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058174CUL)
#define CYREG_TCPWM0_GRP0_CNT46_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581750UL)
#define CYREG_TCPWM0_GRP0_CNT46_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581754UL)
#define CYREG_TCPWM0_GRP0_CNT46_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581770UL)
#define CYREG_TCPWM0_GRP0_CNT46_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581774UL)
#define CYREG_TCPWM0_GRP0_CNT46_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581778UL)
#define CYREG_TCPWM0_GRP0_CNT46_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058177CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT47)
  */
#define CYREG_TCPWM0_GRP0_CNT47_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581780UL)
#define CYREG_TCPWM0_GRP0_CNT47_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581784UL)
#define CYREG_TCPWM0_GRP0_CNT47_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581788UL)
#define CYREG_TCPWM0_GRP0_CNT47_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581790UL)
#define CYREG_TCPWM0_GRP0_CNT47_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581794UL)
#define CYREG_TCPWM0_GRP0_CNT47_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581798UL)
#define CYREG_TCPWM0_GRP0_CNT47_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058179CUL)
#define CYREG_TCPWM0_GRP0_CNT47_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405817A0UL)
#define CYREG_TCPWM0_GRP0_CNT47_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405817A4UL)
#define CYREG_TCPWM0_GRP0_CNT47_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405817B0UL)
#define CYREG_TCPWM0_GRP0_CNT47_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405817C0UL)
#define CYREG_TCPWM0_GRP0_CNT47_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405817C4UL)
#define CYREG_TCPWM0_GRP0_CNT47_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405817C8UL)
#define CYREG_TCPWM0_GRP0_CNT47_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405817CCUL)
#define CYREG_TCPWM0_GRP0_CNT47_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405817D0UL)
#define CYREG_TCPWM0_GRP0_CNT47_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405817D4UL)
#define CYREG_TCPWM0_GRP0_CNT47_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405817F0UL)
#define CYREG_TCPWM0_GRP0_CNT47_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405817F4UL)
#define CYREG_TCPWM0_GRP0_CNT47_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405817F8UL)
#define CYREG_TCPWM0_GRP0_CNT47_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405817FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT48)
  */
#define CYREG_TCPWM0_GRP0_CNT48_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581800UL)
#define CYREG_TCPWM0_GRP0_CNT48_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581804UL)
#define CYREG_TCPWM0_GRP0_CNT48_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581808UL)
#define CYREG_TCPWM0_GRP0_CNT48_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581810UL)
#define CYREG_TCPWM0_GRP0_CNT48_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581814UL)
#define CYREG_TCPWM0_GRP0_CNT48_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581818UL)
#define CYREG_TCPWM0_GRP0_CNT48_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058181CUL)
#define CYREG_TCPWM0_GRP0_CNT48_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581820UL)
#define CYREG_TCPWM0_GRP0_CNT48_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581824UL)
#define CYREG_TCPWM0_GRP0_CNT48_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581830UL)
#define CYREG_TCPWM0_GRP0_CNT48_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581840UL)
#define CYREG_TCPWM0_GRP0_CNT48_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581844UL)
#define CYREG_TCPWM0_GRP0_CNT48_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581848UL)
#define CYREG_TCPWM0_GRP0_CNT48_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058184CUL)
#define CYREG_TCPWM0_GRP0_CNT48_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581850UL)
#define CYREG_TCPWM0_GRP0_CNT48_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581854UL)
#define CYREG_TCPWM0_GRP0_CNT48_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581870UL)
#define CYREG_TCPWM0_GRP0_CNT48_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581874UL)
#define CYREG_TCPWM0_GRP0_CNT48_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581878UL)
#define CYREG_TCPWM0_GRP0_CNT48_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058187CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT49)
  */
#define CYREG_TCPWM0_GRP0_CNT49_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581880UL)
#define CYREG_TCPWM0_GRP0_CNT49_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581884UL)
#define CYREG_TCPWM0_GRP0_CNT49_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581888UL)
#define CYREG_TCPWM0_GRP0_CNT49_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581890UL)
#define CYREG_TCPWM0_GRP0_CNT49_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581894UL)
#define CYREG_TCPWM0_GRP0_CNT49_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581898UL)
#define CYREG_TCPWM0_GRP0_CNT49_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058189CUL)
#define CYREG_TCPWM0_GRP0_CNT49_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405818A0UL)
#define CYREG_TCPWM0_GRP0_CNT49_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405818A4UL)
#define CYREG_TCPWM0_GRP0_CNT49_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405818B0UL)
#define CYREG_TCPWM0_GRP0_CNT49_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405818C0UL)
#define CYREG_TCPWM0_GRP0_CNT49_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405818C4UL)
#define CYREG_TCPWM0_GRP0_CNT49_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405818C8UL)
#define CYREG_TCPWM0_GRP0_CNT49_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405818CCUL)
#define CYREG_TCPWM0_GRP0_CNT49_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405818D0UL)
#define CYREG_TCPWM0_GRP0_CNT49_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405818D4UL)
#define CYREG_TCPWM0_GRP0_CNT49_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405818F0UL)
#define CYREG_TCPWM0_GRP0_CNT49_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405818F4UL)
#define CYREG_TCPWM0_GRP0_CNT49_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405818F8UL)
#define CYREG_TCPWM0_GRP0_CNT49_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405818FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT50)
  */
#define CYREG_TCPWM0_GRP0_CNT50_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581900UL)
#define CYREG_TCPWM0_GRP0_CNT50_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581904UL)
#define CYREG_TCPWM0_GRP0_CNT50_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581908UL)
#define CYREG_TCPWM0_GRP0_CNT50_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581910UL)
#define CYREG_TCPWM0_GRP0_CNT50_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581914UL)
#define CYREG_TCPWM0_GRP0_CNT50_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581918UL)
#define CYREG_TCPWM0_GRP0_CNT50_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058191CUL)
#define CYREG_TCPWM0_GRP0_CNT50_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581920UL)
#define CYREG_TCPWM0_GRP0_CNT50_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581924UL)
#define CYREG_TCPWM0_GRP0_CNT50_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581930UL)
#define CYREG_TCPWM0_GRP0_CNT50_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581940UL)
#define CYREG_TCPWM0_GRP0_CNT50_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581944UL)
#define CYREG_TCPWM0_GRP0_CNT50_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581948UL)
#define CYREG_TCPWM0_GRP0_CNT50_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058194CUL)
#define CYREG_TCPWM0_GRP0_CNT50_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581950UL)
#define CYREG_TCPWM0_GRP0_CNT50_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581954UL)
#define CYREG_TCPWM0_GRP0_CNT50_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581970UL)
#define CYREG_TCPWM0_GRP0_CNT50_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581974UL)
#define CYREG_TCPWM0_GRP0_CNT50_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581978UL)
#define CYREG_TCPWM0_GRP0_CNT50_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058197CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT51)
  */
#define CYREG_TCPWM0_GRP0_CNT51_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581980UL)
#define CYREG_TCPWM0_GRP0_CNT51_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581984UL)
#define CYREG_TCPWM0_GRP0_CNT51_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581988UL)
#define CYREG_TCPWM0_GRP0_CNT51_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581990UL)
#define CYREG_TCPWM0_GRP0_CNT51_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581994UL)
#define CYREG_TCPWM0_GRP0_CNT51_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581998UL)
#define CYREG_TCPWM0_GRP0_CNT51_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058199CUL)
#define CYREG_TCPWM0_GRP0_CNT51_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405819A0UL)
#define CYREG_TCPWM0_GRP0_CNT51_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405819A4UL)
#define CYREG_TCPWM0_GRP0_CNT51_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405819B0UL)
#define CYREG_TCPWM0_GRP0_CNT51_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405819C0UL)
#define CYREG_TCPWM0_GRP0_CNT51_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405819C4UL)
#define CYREG_TCPWM0_GRP0_CNT51_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405819C8UL)
#define CYREG_TCPWM0_GRP0_CNT51_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405819CCUL)
#define CYREG_TCPWM0_GRP0_CNT51_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405819D0UL)
#define CYREG_TCPWM0_GRP0_CNT51_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405819D4UL)
#define CYREG_TCPWM0_GRP0_CNT51_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405819F0UL)
#define CYREG_TCPWM0_GRP0_CNT51_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405819F4UL)
#define CYREG_TCPWM0_GRP0_CNT51_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405819F8UL)
#define CYREG_TCPWM0_GRP0_CNT51_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405819FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT52)
  */
#define CYREG_TCPWM0_GRP0_CNT52_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581A00UL)
#define CYREG_TCPWM0_GRP0_CNT52_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581A04UL)
#define CYREG_TCPWM0_GRP0_CNT52_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581A08UL)
#define CYREG_TCPWM0_GRP0_CNT52_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581A10UL)
#define CYREG_TCPWM0_GRP0_CNT52_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581A14UL)
#define CYREG_TCPWM0_GRP0_CNT52_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581A18UL)
#define CYREG_TCPWM0_GRP0_CNT52_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40581A1CUL)
#define CYREG_TCPWM0_GRP0_CNT52_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581A20UL)
#define CYREG_TCPWM0_GRP0_CNT52_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581A24UL)
#define CYREG_TCPWM0_GRP0_CNT52_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581A30UL)
#define CYREG_TCPWM0_GRP0_CNT52_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581A40UL)
#define CYREG_TCPWM0_GRP0_CNT52_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581A44UL)
#define CYREG_TCPWM0_GRP0_CNT52_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581A48UL)
#define CYREG_TCPWM0_GRP0_CNT52_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40581A4CUL)
#define CYREG_TCPWM0_GRP0_CNT52_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581A50UL)
#define CYREG_TCPWM0_GRP0_CNT52_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581A54UL)
#define CYREG_TCPWM0_GRP0_CNT52_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581A70UL)
#define CYREG_TCPWM0_GRP0_CNT52_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581A74UL)
#define CYREG_TCPWM0_GRP0_CNT52_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581A78UL)
#define CYREG_TCPWM0_GRP0_CNT52_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40581A7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT53)
  */
#define CYREG_TCPWM0_GRP0_CNT53_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581A80UL)
#define CYREG_TCPWM0_GRP0_CNT53_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581A84UL)
#define CYREG_TCPWM0_GRP0_CNT53_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581A88UL)
#define CYREG_TCPWM0_GRP0_CNT53_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581A90UL)
#define CYREG_TCPWM0_GRP0_CNT53_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581A94UL)
#define CYREG_TCPWM0_GRP0_CNT53_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581A98UL)
#define CYREG_TCPWM0_GRP0_CNT53_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40581A9CUL)
#define CYREG_TCPWM0_GRP0_CNT53_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581AA0UL)
#define CYREG_TCPWM0_GRP0_CNT53_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581AA4UL)
#define CYREG_TCPWM0_GRP0_CNT53_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581AB0UL)
#define CYREG_TCPWM0_GRP0_CNT53_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581AC0UL)
#define CYREG_TCPWM0_GRP0_CNT53_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581AC4UL)
#define CYREG_TCPWM0_GRP0_CNT53_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581AC8UL)
#define CYREG_TCPWM0_GRP0_CNT53_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40581ACCUL)
#define CYREG_TCPWM0_GRP0_CNT53_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581AD0UL)
#define CYREG_TCPWM0_GRP0_CNT53_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581AD4UL)
#define CYREG_TCPWM0_GRP0_CNT53_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581AF0UL)
#define CYREG_TCPWM0_GRP0_CNT53_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581AF4UL)
#define CYREG_TCPWM0_GRP0_CNT53_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581AF8UL)
#define CYREG_TCPWM0_GRP0_CNT53_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40581AFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT54)
  */
#define CYREG_TCPWM0_GRP0_CNT54_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581B00UL)
#define CYREG_TCPWM0_GRP0_CNT54_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581B04UL)
#define CYREG_TCPWM0_GRP0_CNT54_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581B08UL)
#define CYREG_TCPWM0_GRP0_CNT54_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581B10UL)
#define CYREG_TCPWM0_GRP0_CNT54_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581B14UL)
#define CYREG_TCPWM0_GRP0_CNT54_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581B18UL)
#define CYREG_TCPWM0_GRP0_CNT54_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40581B1CUL)
#define CYREG_TCPWM0_GRP0_CNT54_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581B20UL)
#define CYREG_TCPWM0_GRP0_CNT54_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581B24UL)
#define CYREG_TCPWM0_GRP0_CNT54_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581B30UL)
#define CYREG_TCPWM0_GRP0_CNT54_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581B40UL)
#define CYREG_TCPWM0_GRP0_CNT54_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581B44UL)
#define CYREG_TCPWM0_GRP0_CNT54_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581B48UL)
#define CYREG_TCPWM0_GRP0_CNT54_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40581B4CUL)
#define CYREG_TCPWM0_GRP0_CNT54_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581B50UL)
#define CYREG_TCPWM0_GRP0_CNT54_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581B54UL)
#define CYREG_TCPWM0_GRP0_CNT54_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581B70UL)
#define CYREG_TCPWM0_GRP0_CNT54_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581B74UL)
#define CYREG_TCPWM0_GRP0_CNT54_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581B78UL)
#define CYREG_TCPWM0_GRP0_CNT54_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40581B7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT55)
  */
#define CYREG_TCPWM0_GRP0_CNT55_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581B80UL)
#define CYREG_TCPWM0_GRP0_CNT55_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581B84UL)
#define CYREG_TCPWM0_GRP0_CNT55_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581B88UL)
#define CYREG_TCPWM0_GRP0_CNT55_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581B90UL)
#define CYREG_TCPWM0_GRP0_CNT55_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581B94UL)
#define CYREG_TCPWM0_GRP0_CNT55_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581B98UL)
#define CYREG_TCPWM0_GRP0_CNT55_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40581B9CUL)
#define CYREG_TCPWM0_GRP0_CNT55_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581BA0UL)
#define CYREG_TCPWM0_GRP0_CNT55_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581BA4UL)
#define CYREG_TCPWM0_GRP0_CNT55_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581BB0UL)
#define CYREG_TCPWM0_GRP0_CNT55_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581BC0UL)
#define CYREG_TCPWM0_GRP0_CNT55_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581BC4UL)
#define CYREG_TCPWM0_GRP0_CNT55_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581BC8UL)
#define CYREG_TCPWM0_GRP0_CNT55_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40581BCCUL)
#define CYREG_TCPWM0_GRP0_CNT55_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581BD0UL)
#define CYREG_TCPWM0_GRP0_CNT55_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581BD4UL)
#define CYREG_TCPWM0_GRP0_CNT55_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581BF0UL)
#define CYREG_TCPWM0_GRP0_CNT55_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581BF4UL)
#define CYREG_TCPWM0_GRP0_CNT55_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581BF8UL)
#define CYREG_TCPWM0_GRP0_CNT55_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40581BFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT56)
  */
#define CYREG_TCPWM0_GRP0_CNT56_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581C00UL)
#define CYREG_TCPWM0_GRP0_CNT56_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581C04UL)
#define CYREG_TCPWM0_GRP0_CNT56_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581C08UL)
#define CYREG_TCPWM0_GRP0_CNT56_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581C10UL)
#define CYREG_TCPWM0_GRP0_CNT56_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581C14UL)
#define CYREG_TCPWM0_GRP0_CNT56_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581C18UL)
#define CYREG_TCPWM0_GRP0_CNT56_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40581C1CUL)
#define CYREG_TCPWM0_GRP0_CNT56_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581C20UL)
#define CYREG_TCPWM0_GRP0_CNT56_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581C24UL)
#define CYREG_TCPWM0_GRP0_CNT56_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581C30UL)
#define CYREG_TCPWM0_GRP0_CNT56_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581C40UL)
#define CYREG_TCPWM0_GRP0_CNT56_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581C44UL)
#define CYREG_TCPWM0_GRP0_CNT56_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581C48UL)
#define CYREG_TCPWM0_GRP0_CNT56_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40581C4CUL)
#define CYREG_TCPWM0_GRP0_CNT56_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581C50UL)
#define CYREG_TCPWM0_GRP0_CNT56_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581C54UL)
#define CYREG_TCPWM0_GRP0_CNT56_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581C70UL)
#define CYREG_TCPWM0_GRP0_CNT56_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581C74UL)
#define CYREG_TCPWM0_GRP0_CNT56_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581C78UL)
#define CYREG_TCPWM0_GRP0_CNT56_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40581C7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT57)
  */
#define CYREG_TCPWM0_GRP0_CNT57_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581C80UL)
#define CYREG_TCPWM0_GRP0_CNT57_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581C84UL)
#define CYREG_TCPWM0_GRP0_CNT57_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581C88UL)
#define CYREG_TCPWM0_GRP0_CNT57_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581C90UL)
#define CYREG_TCPWM0_GRP0_CNT57_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581C94UL)
#define CYREG_TCPWM0_GRP0_CNT57_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581C98UL)
#define CYREG_TCPWM0_GRP0_CNT57_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40581C9CUL)
#define CYREG_TCPWM0_GRP0_CNT57_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581CA0UL)
#define CYREG_TCPWM0_GRP0_CNT57_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581CA4UL)
#define CYREG_TCPWM0_GRP0_CNT57_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581CB0UL)
#define CYREG_TCPWM0_GRP0_CNT57_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581CC0UL)
#define CYREG_TCPWM0_GRP0_CNT57_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581CC4UL)
#define CYREG_TCPWM0_GRP0_CNT57_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581CC8UL)
#define CYREG_TCPWM0_GRP0_CNT57_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40581CCCUL)
#define CYREG_TCPWM0_GRP0_CNT57_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581CD0UL)
#define CYREG_TCPWM0_GRP0_CNT57_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581CD4UL)
#define CYREG_TCPWM0_GRP0_CNT57_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581CF0UL)
#define CYREG_TCPWM0_GRP0_CNT57_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581CF4UL)
#define CYREG_TCPWM0_GRP0_CNT57_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581CF8UL)
#define CYREG_TCPWM0_GRP0_CNT57_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40581CFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT58)
  */
#define CYREG_TCPWM0_GRP0_CNT58_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581D00UL)
#define CYREG_TCPWM0_GRP0_CNT58_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581D04UL)
#define CYREG_TCPWM0_GRP0_CNT58_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581D08UL)
#define CYREG_TCPWM0_GRP0_CNT58_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581D10UL)
#define CYREG_TCPWM0_GRP0_CNT58_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581D14UL)
#define CYREG_TCPWM0_GRP0_CNT58_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581D18UL)
#define CYREG_TCPWM0_GRP0_CNT58_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40581D1CUL)
#define CYREG_TCPWM0_GRP0_CNT58_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581D20UL)
#define CYREG_TCPWM0_GRP0_CNT58_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581D24UL)
#define CYREG_TCPWM0_GRP0_CNT58_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581D30UL)
#define CYREG_TCPWM0_GRP0_CNT58_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581D40UL)
#define CYREG_TCPWM0_GRP0_CNT58_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581D44UL)
#define CYREG_TCPWM0_GRP0_CNT58_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581D48UL)
#define CYREG_TCPWM0_GRP0_CNT58_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40581D4CUL)
#define CYREG_TCPWM0_GRP0_CNT58_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581D50UL)
#define CYREG_TCPWM0_GRP0_CNT58_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581D54UL)
#define CYREG_TCPWM0_GRP0_CNT58_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581D70UL)
#define CYREG_TCPWM0_GRP0_CNT58_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581D74UL)
#define CYREG_TCPWM0_GRP0_CNT58_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581D78UL)
#define CYREG_TCPWM0_GRP0_CNT58_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40581D7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT59)
  */
#define CYREG_TCPWM0_GRP0_CNT59_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581D80UL)
#define CYREG_TCPWM0_GRP0_CNT59_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581D84UL)
#define CYREG_TCPWM0_GRP0_CNT59_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581D88UL)
#define CYREG_TCPWM0_GRP0_CNT59_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581D90UL)
#define CYREG_TCPWM0_GRP0_CNT59_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581D94UL)
#define CYREG_TCPWM0_GRP0_CNT59_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581D98UL)
#define CYREG_TCPWM0_GRP0_CNT59_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40581D9CUL)
#define CYREG_TCPWM0_GRP0_CNT59_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581DA0UL)
#define CYREG_TCPWM0_GRP0_CNT59_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581DA4UL)
#define CYREG_TCPWM0_GRP0_CNT59_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581DB0UL)
#define CYREG_TCPWM0_GRP0_CNT59_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581DC0UL)
#define CYREG_TCPWM0_GRP0_CNT59_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581DC4UL)
#define CYREG_TCPWM0_GRP0_CNT59_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581DC8UL)
#define CYREG_TCPWM0_GRP0_CNT59_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40581DCCUL)
#define CYREG_TCPWM0_GRP0_CNT59_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581DD0UL)
#define CYREG_TCPWM0_GRP0_CNT59_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581DD4UL)
#define CYREG_TCPWM0_GRP0_CNT59_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581DF0UL)
#define CYREG_TCPWM0_GRP0_CNT59_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581DF4UL)
#define CYREG_TCPWM0_GRP0_CNT59_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581DF8UL)
#define CYREG_TCPWM0_GRP0_CNT59_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40581DFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT60)
  */
#define CYREG_TCPWM0_GRP0_CNT60_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581E00UL)
#define CYREG_TCPWM0_GRP0_CNT60_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581E04UL)
#define CYREG_TCPWM0_GRP0_CNT60_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581E08UL)
#define CYREG_TCPWM0_GRP0_CNT60_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581E10UL)
#define CYREG_TCPWM0_GRP0_CNT60_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581E14UL)
#define CYREG_TCPWM0_GRP0_CNT60_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581E18UL)
#define CYREG_TCPWM0_GRP0_CNT60_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40581E1CUL)
#define CYREG_TCPWM0_GRP0_CNT60_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581E20UL)
#define CYREG_TCPWM0_GRP0_CNT60_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581E24UL)
#define CYREG_TCPWM0_GRP0_CNT60_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581E30UL)
#define CYREG_TCPWM0_GRP0_CNT60_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581E40UL)
#define CYREG_TCPWM0_GRP0_CNT60_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581E44UL)
#define CYREG_TCPWM0_GRP0_CNT60_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581E48UL)
#define CYREG_TCPWM0_GRP0_CNT60_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40581E4CUL)
#define CYREG_TCPWM0_GRP0_CNT60_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581E50UL)
#define CYREG_TCPWM0_GRP0_CNT60_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581E54UL)
#define CYREG_TCPWM0_GRP0_CNT60_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581E70UL)
#define CYREG_TCPWM0_GRP0_CNT60_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581E74UL)
#define CYREG_TCPWM0_GRP0_CNT60_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581E78UL)
#define CYREG_TCPWM0_GRP0_CNT60_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40581E7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT61)
  */
#define CYREG_TCPWM0_GRP0_CNT61_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581E80UL)
#define CYREG_TCPWM0_GRP0_CNT61_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581E84UL)
#define CYREG_TCPWM0_GRP0_CNT61_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581E88UL)
#define CYREG_TCPWM0_GRP0_CNT61_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581E90UL)
#define CYREG_TCPWM0_GRP0_CNT61_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581E94UL)
#define CYREG_TCPWM0_GRP0_CNT61_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581E98UL)
#define CYREG_TCPWM0_GRP0_CNT61_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40581E9CUL)
#define CYREG_TCPWM0_GRP0_CNT61_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581EA0UL)
#define CYREG_TCPWM0_GRP0_CNT61_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581EA4UL)
#define CYREG_TCPWM0_GRP0_CNT61_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581EB0UL)
#define CYREG_TCPWM0_GRP0_CNT61_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581EC0UL)
#define CYREG_TCPWM0_GRP0_CNT61_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581EC4UL)
#define CYREG_TCPWM0_GRP0_CNT61_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581EC8UL)
#define CYREG_TCPWM0_GRP0_CNT61_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40581ECCUL)
#define CYREG_TCPWM0_GRP0_CNT61_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581ED0UL)
#define CYREG_TCPWM0_GRP0_CNT61_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581ED4UL)
#define CYREG_TCPWM0_GRP0_CNT61_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581EF0UL)
#define CYREG_TCPWM0_GRP0_CNT61_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581EF4UL)
#define CYREG_TCPWM0_GRP0_CNT61_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581EF8UL)
#define CYREG_TCPWM0_GRP0_CNT61_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40581EFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT62)
  */
#define CYREG_TCPWM0_GRP0_CNT62_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40581F00UL)
#define CYREG_TCPWM0_GRP0_CNT62_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40581F04UL)
#define CYREG_TCPWM0_GRP0_CNT62_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40581F08UL)
#define CYREG_TCPWM0_GRP0_CNT62_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40581F10UL)
#define CYREG_TCPWM0_GRP0_CNT62_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40581F14UL)
#define CYREG_TCPWM0_GRP0_CNT62_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40581F18UL)
#define CYREG_TCPWM0_GRP0_CNT62_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40581F1CUL)
#define CYREG_TCPWM0_GRP0_CNT62_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40581F20UL)
#define CYREG_TCPWM0_GRP0_CNT62_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40581F24UL)
#define CYREG_TCPWM0_GRP0_CNT62_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40581F30UL)
#define CYREG_TCPWM0_GRP0_CNT62_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40581F40UL)
#define CYREG_TCPWM0_GRP0_CNT62_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40581F44UL)
#define CYREG_TCPWM0_GRP0_CNT62_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40581F48UL)
#define CYREG_TCPWM0_GRP0_CNT62_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40581F4CUL)
#define CYREG_TCPWM0_GRP0_CNT62_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40581F50UL)
#define CYREG_TCPWM0_GRP0_CNT62_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40581F54UL)
#define CYREG_TCPWM0_GRP0_CNT62_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40581F70UL)
#define CYREG_TCPWM0_GRP0_CNT62_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40581F74UL)
#define CYREG_TCPWM0_GRP0_CNT62_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40581F78UL)
#define CYREG_TCPWM0_GRP0_CNT62_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40581F7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT0)
  */
#define CYREG_TCPWM0_GRP1_CNT0_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40588000UL)
#define CYREG_TCPWM0_GRP1_CNT0_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40588004UL)
#define CYREG_TCPWM0_GRP1_CNT0_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40588008UL)
#define CYREG_TCPWM0_GRP1_CNT0_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40588010UL)
#define CYREG_TCPWM0_GRP1_CNT0_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40588014UL)
#define CYREG_TCPWM0_GRP1_CNT0_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40588018UL)
#define CYREG_TCPWM0_GRP1_CNT0_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058801CUL)
#define CYREG_TCPWM0_GRP1_CNT0_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40588020UL)
#define CYREG_TCPWM0_GRP1_CNT0_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40588024UL)
#define CYREG_TCPWM0_GRP1_CNT0_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x40588028UL)
#define CYREG_TCPWM0_GRP1_CNT0_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x4058802CUL)
#define CYREG_TCPWM0_GRP1_CNT0_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40588030UL)
#define CYREG_TCPWM0_GRP1_CNT0_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40588040UL)
#define CYREG_TCPWM0_GRP1_CNT0_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40588044UL)
#define CYREG_TCPWM0_GRP1_CNT0_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40588048UL)
#define CYREG_TCPWM0_GRP1_CNT0_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058804CUL)
#define CYREG_TCPWM0_GRP1_CNT0_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40588050UL)
#define CYREG_TCPWM0_GRP1_CNT0_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40588054UL)
#define CYREG_TCPWM0_GRP1_CNT0_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40588070UL)
#define CYREG_TCPWM0_GRP1_CNT0_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40588074UL)
#define CYREG_TCPWM0_GRP1_CNT0_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40588078UL)
#define CYREG_TCPWM0_GRP1_CNT0_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058807CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT1)
  */
#define CYREG_TCPWM0_GRP1_CNT1_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40588080UL)
#define CYREG_TCPWM0_GRP1_CNT1_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40588084UL)
#define CYREG_TCPWM0_GRP1_CNT1_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40588088UL)
#define CYREG_TCPWM0_GRP1_CNT1_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40588090UL)
#define CYREG_TCPWM0_GRP1_CNT1_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40588094UL)
#define CYREG_TCPWM0_GRP1_CNT1_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40588098UL)
#define CYREG_TCPWM0_GRP1_CNT1_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058809CUL)
#define CYREG_TCPWM0_GRP1_CNT1_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405880A0UL)
#define CYREG_TCPWM0_GRP1_CNT1_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405880A4UL)
#define CYREG_TCPWM0_GRP1_CNT1_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x405880A8UL)
#define CYREG_TCPWM0_GRP1_CNT1_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x405880ACUL)
#define CYREG_TCPWM0_GRP1_CNT1_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405880B0UL)
#define CYREG_TCPWM0_GRP1_CNT1_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405880C0UL)
#define CYREG_TCPWM0_GRP1_CNT1_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405880C4UL)
#define CYREG_TCPWM0_GRP1_CNT1_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405880C8UL)
#define CYREG_TCPWM0_GRP1_CNT1_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405880CCUL)
#define CYREG_TCPWM0_GRP1_CNT1_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405880D0UL)
#define CYREG_TCPWM0_GRP1_CNT1_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405880D4UL)
#define CYREG_TCPWM0_GRP1_CNT1_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405880F0UL)
#define CYREG_TCPWM0_GRP1_CNT1_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405880F4UL)
#define CYREG_TCPWM0_GRP1_CNT1_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405880F8UL)
#define CYREG_TCPWM0_GRP1_CNT1_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405880FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT2)
  */
#define CYREG_TCPWM0_GRP1_CNT2_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40588100UL)
#define CYREG_TCPWM0_GRP1_CNT2_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40588104UL)
#define CYREG_TCPWM0_GRP1_CNT2_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40588108UL)
#define CYREG_TCPWM0_GRP1_CNT2_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40588110UL)
#define CYREG_TCPWM0_GRP1_CNT2_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40588114UL)
#define CYREG_TCPWM0_GRP1_CNT2_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40588118UL)
#define CYREG_TCPWM0_GRP1_CNT2_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058811CUL)
#define CYREG_TCPWM0_GRP1_CNT2_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40588120UL)
#define CYREG_TCPWM0_GRP1_CNT2_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40588124UL)
#define CYREG_TCPWM0_GRP1_CNT2_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x40588128UL)
#define CYREG_TCPWM0_GRP1_CNT2_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x4058812CUL)
#define CYREG_TCPWM0_GRP1_CNT2_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40588130UL)
#define CYREG_TCPWM0_GRP1_CNT2_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40588140UL)
#define CYREG_TCPWM0_GRP1_CNT2_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40588144UL)
#define CYREG_TCPWM0_GRP1_CNT2_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40588148UL)
#define CYREG_TCPWM0_GRP1_CNT2_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058814CUL)
#define CYREG_TCPWM0_GRP1_CNT2_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40588150UL)
#define CYREG_TCPWM0_GRP1_CNT2_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40588154UL)
#define CYREG_TCPWM0_GRP1_CNT2_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40588170UL)
#define CYREG_TCPWM0_GRP1_CNT2_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40588174UL)
#define CYREG_TCPWM0_GRP1_CNT2_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40588178UL)
#define CYREG_TCPWM0_GRP1_CNT2_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058817CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT3)
  */
#define CYREG_TCPWM0_GRP1_CNT3_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40588180UL)
#define CYREG_TCPWM0_GRP1_CNT3_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40588184UL)
#define CYREG_TCPWM0_GRP1_CNT3_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40588188UL)
#define CYREG_TCPWM0_GRP1_CNT3_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40588190UL)
#define CYREG_TCPWM0_GRP1_CNT3_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40588194UL)
#define CYREG_TCPWM0_GRP1_CNT3_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40588198UL)
#define CYREG_TCPWM0_GRP1_CNT3_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058819CUL)
#define CYREG_TCPWM0_GRP1_CNT3_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405881A0UL)
#define CYREG_TCPWM0_GRP1_CNT3_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405881A4UL)
#define CYREG_TCPWM0_GRP1_CNT3_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x405881A8UL)
#define CYREG_TCPWM0_GRP1_CNT3_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x405881ACUL)
#define CYREG_TCPWM0_GRP1_CNT3_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405881B0UL)
#define CYREG_TCPWM0_GRP1_CNT3_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405881C0UL)
#define CYREG_TCPWM0_GRP1_CNT3_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405881C4UL)
#define CYREG_TCPWM0_GRP1_CNT3_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405881C8UL)
#define CYREG_TCPWM0_GRP1_CNT3_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405881CCUL)
#define CYREG_TCPWM0_GRP1_CNT3_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405881D0UL)
#define CYREG_TCPWM0_GRP1_CNT3_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405881D4UL)
#define CYREG_TCPWM0_GRP1_CNT3_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405881F0UL)
#define CYREG_TCPWM0_GRP1_CNT3_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405881F4UL)
#define CYREG_TCPWM0_GRP1_CNT3_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405881F8UL)
#define CYREG_TCPWM0_GRP1_CNT3_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405881FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT4)
  */
#define CYREG_TCPWM0_GRP1_CNT4_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40588200UL)
#define CYREG_TCPWM0_GRP1_CNT4_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40588204UL)
#define CYREG_TCPWM0_GRP1_CNT4_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40588208UL)
#define CYREG_TCPWM0_GRP1_CNT4_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40588210UL)
#define CYREG_TCPWM0_GRP1_CNT4_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40588214UL)
#define CYREG_TCPWM0_GRP1_CNT4_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40588218UL)
#define CYREG_TCPWM0_GRP1_CNT4_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058821CUL)
#define CYREG_TCPWM0_GRP1_CNT4_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40588220UL)
#define CYREG_TCPWM0_GRP1_CNT4_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40588224UL)
#define CYREG_TCPWM0_GRP1_CNT4_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x40588228UL)
#define CYREG_TCPWM0_GRP1_CNT4_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x4058822CUL)
#define CYREG_TCPWM0_GRP1_CNT4_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40588230UL)
#define CYREG_TCPWM0_GRP1_CNT4_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40588240UL)
#define CYREG_TCPWM0_GRP1_CNT4_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40588244UL)
#define CYREG_TCPWM0_GRP1_CNT4_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40588248UL)
#define CYREG_TCPWM0_GRP1_CNT4_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058824CUL)
#define CYREG_TCPWM0_GRP1_CNT4_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40588250UL)
#define CYREG_TCPWM0_GRP1_CNT4_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40588254UL)
#define CYREG_TCPWM0_GRP1_CNT4_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40588270UL)
#define CYREG_TCPWM0_GRP1_CNT4_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40588274UL)
#define CYREG_TCPWM0_GRP1_CNT4_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40588278UL)
#define CYREG_TCPWM0_GRP1_CNT4_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058827CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT5)
  */
#define CYREG_TCPWM0_GRP1_CNT5_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40588280UL)
#define CYREG_TCPWM0_GRP1_CNT5_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40588284UL)
#define CYREG_TCPWM0_GRP1_CNT5_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40588288UL)
#define CYREG_TCPWM0_GRP1_CNT5_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40588290UL)
#define CYREG_TCPWM0_GRP1_CNT5_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40588294UL)
#define CYREG_TCPWM0_GRP1_CNT5_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40588298UL)
#define CYREG_TCPWM0_GRP1_CNT5_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058829CUL)
#define CYREG_TCPWM0_GRP1_CNT5_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405882A0UL)
#define CYREG_TCPWM0_GRP1_CNT5_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405882A4UL)
#define CYREG_TCPWM0_GRP1_CNT5_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x405882A8UL)
#define CYREG_TCPWM0_GRP1_CNT5_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x405882ACUL)
#define CYREG_TCPWM0_GRP1_CNT5_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405882B0UL)
#define CYREG_TCPWM0_GRP1_CNT5_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405882C0UL)
#define CYREG_TCPWM0_GRP1_CNT5_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405882C4UL)
#define CYREG_TCPWM0_GRP1_CNT5_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405882C8UL)
#define CYREG_TCPWM0_GRP1_CNT5_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405882CCUL)
#define CYREG_TCPWM0_GRP1_CNT5_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405882D0UL)
#define CYREG_TCPWM0_GRP1_CNT5_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405882D4UL)
#define CYREG_TCPWM0_GRP1_CNT5_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405882F0UL)
#define CYREG_TCPWM0_GRP1_CNT5_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405882F4UL)
#define CYREG_TCPWM0_GRP1_CNT5_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405882F8UL)
#define CYREG_TCPWM0_GRP1_CNT5_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405882FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT6)
  */
#define CYREG_TCPWM0_GRP1_CNT6_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40588300UL)
#define CYREG_TCPWM0_GRP1_CNT6_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40588304UL)
#define CYREG_TCPWM0_GRP1_CNT6_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40588308UL)
#define CYREG_TCPWM0_GRP1_CNT6_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40588310UL)
#define CYREG_TCPWM0_GRP1_CNT6_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40588314UL)
#define CYREG_TCPWM0_GRP1_CNT6_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40588318UL)
#define CYREG_TCPWM0_GRP1_CNT6_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058831CUL)
#define CYREG_TCPWM0_GRP1_CNT6_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40588320UL)
#define CYREG_TCPWM0_GRP1_CNT6_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40588324UL)
#define CYREG_TCPWM0_GRP1_CNT6_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x40588328UL)
#define CYREG_TCPWM0_GRP1_CNT6_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x4058832CUL)
#define CYREG_TCPWM0_GRP1_CNT6_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40588330UL)
#define CYREG_TCPWM0_GRP1_CNT6_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40588340UL)
#define CYREG_TCPWM0_GRP1_CNT6_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40588344UL)
#define CYREG_TCPWM0_GRP1_CNT6_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40588348UL)
#define CYREG_TCPWM0_GRP1_CNT6_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058834CUL)
#define CYREG_TCPWM0_GRP1_CNT6_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40588350UL)
#define CYREG_TCPWM0_GRP1_CNT6_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40588354UL)
#define CYREG_TCPWM0_GRP1_CNT6_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40588370UL)
#define CYREG_TCPWM0_GRP1_CNT6_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40588374UL)
#define CYREG_TCPWM0_GRP1_CNT6_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40588378UL)
#define CYREG_TCPWM0_GRP1_CNT6_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058837CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT7)
  */
#define CYREG_TCPWM0_GRP1_CNT7_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40588380UL)
#define CYREG_TCPWM0_GRP1_CNT7_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40588384UL)
#define CYREG_TCPWM0_GRP1_CNT7_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40588388UL)
#define CYREG_TCPWM0_GRP1_CNT7_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40588390UL)
#define CYREG_TCPWM0_GRP1_CNT7_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40588394UL)
#define CYREG_TCPWM0_GRP1_CNT7_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40588398UL)
#define CYREG_TCPWM0_GRP1_CNT7_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058839CUL)
#define CYREG_TCPWM0_GRP1_CNT7_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405883A0UL)
#define CYREG_TCPWM0_GRP1_CNT7_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405883A4UL)
#define CYREG_TCPWM0_GRP1_CNT7_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x405883A8UL)
#define CYREG_TCPWM0_GRP1_CNT7_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x405883ACUL)
#define CYREG_TCPWM0_GRP1_CNT7_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405883B0UL)
#define CYREG_TCPWM0_GRP1_CNT7_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405883C0UL)
#define CYREG_TCPWM0_GRP1_CNT7_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405883C4UL)
#define CYREG_TCPWM0_GRP1_CNT7_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405883C8UL)
#define CYREG_TCPWM0_GRP1_CNT7_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405883CCUL)
#define CYREG_TCPWM0_GRP1_CNT7_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405883D0UL)
#define CYREG_TCPWM0_GRP1_CNT7_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405883D4UL)
#define CYREG_TCPWM0_GRP1_CNT7_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405883F0UL)
#define CYREG_TCPWM0_GRP1_CNT7_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405883F4UL)
#define CYREG_TCPWM0_GRP1_CNT7_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405883F8UL)
#define CYREG_TCPWM0_GRP1_CNT7_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405883FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT8)
  */
#define CYREG_TCPWM0_GRP1_CNT8_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40588400UL)
#define CYREG_TCPWM0_GRP1_CNT8_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40588404UL)
#define CYREG_TCPWM0_GRP1_CNT8_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40588408UL)
#define CYREG_TCPWM0_GRP1_CNT8_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40588410UL)
#define CYREG_TCPWM0_GRP1_CNT8_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40588414UL)
#define CYREG_TCPWM0_GRP1_CNT8_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40588418UL)
#define CYREG_TCPWM0_GRP1_CNT8_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058841CUL)
#define CYREG_TCPWM0_GRP1_CNT8_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40588420UL)
#define CYREG_TCPWM0_GRP1_CNT8_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40588424UL)
#define CYREG_TCPWM0_GRP1_CNT8_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x40588428UL)
#define CYREG_TCPWM0_GRP1_CNT8_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x4058842CUL)
#define CYREG_TCPWM0_GRP1_CNT8_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40588430UL)
#define CYREG_TCPWM0_GRP1_CNT8_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40588440UL)
#define CYREG_TCPWM0_GRP1_CNT8_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40588444UL)
#define CYREG_TCPWM0_GRP1_CNT8_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40588448UL)
#define CYREG_TCPWM0_GRP1_CNT8_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058844CUL)
#define CYREG_TCPWM0_GRP1_CNT8_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40588450UL)
#define CYREG_TCPWM0_GRP1_CNT8_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40588454UL)
#define CYREG_TCPWM0_GRP1_CNT8_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40588470UL)
#define CYREG_TCPWM0_GRP1_CNT8_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40588474UL)
#define CYREG_TCPWM0_GRP1_CNT8_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40588478UL)
#define CYREG_TCPWM0_GRP1_CNT8_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058847CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT9)
  */
#define CYREG_TCPWM0_GRP1_CNT9_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40588480UL)
#define CYREG_TCPWM0_GRP1_CNT9_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40588484UL)
#define CYREG_TCPWM0_GRP1_CNT9_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40588488UL)
#define CYREG_TCPWM0_GRP1_CNT9_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40588490UL)
#define CYREG_TCPWM0_GRP1_CNT9_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40588494UL)
#define CYREG_TCPWM0_GRP1_CNT9_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40588498UL)
#define CYREG_TCPWM0_GRP1_CNT9_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058849CUL)
#define CYREG_TCPWM0_GRP1_CNT9_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405884A0UL)
#define CYREG_TCPWM0_GRP1_CNT9_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405884A4UL)
#define CYREG_TCPWM0_GRP1_CNT9_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x405884A8UL)
#define CYREG_TCPWM0_GRP1_CNT9_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x405884ACUL)
#define CYREG_TCPWM0_GRP1_CNT9_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405884B0UL)
#define CYREG_TCPWM0_GRP1_CNT9_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405884C0UL)
#define CYREG_TCPWM0_GRP1_CNT9_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405884C4UL)
#define CYREG_TCPWM0_GRP1_CNT9_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405884C8UL)
#define CYREG_TCPWM0_GRP1_CNT9_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405884CCUL)
#define CYREG_TCPWM0_GRP1_CNT9_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405884D0UL)
#define CYREG_TCPWM0_GRP1_CNT9_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405884D4UL)
#define CYREG_TCPWM0_GRP1_CNT9_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405884F0UL)
#define CYREG_TCPWM0_GRP1_CNT9_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405884F4UL)
#define CYREG_TCPWM0_GRP1_CNT9_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405884F8UL)
#define CYREG_TCPWM0_GRP1_CNT9_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405884FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT10)
  */
#define CYREG_TCPWM0_GRP1_CNT10_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40588500UL)
#define CYREG_TCPWM0_GRP1_CNT10_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40588504UL)
#define CYREG_TCPWM0_GRP1_CNT10_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40588508UL)
#define CYREG_TCPWM0_GRP1_CNT10_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40588510UL)
#define CYREG_TCPWM0_GRP1_CNT10_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40588514UL)
#define CYREG_TCPWM0_GRP1_CNT10_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40588518UL)
#define CYREG_TCPWM0_GRP1_CNT10_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058851CUL)
#define CYREG_TCPWM0_GRP1_CNT10_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40588520UL)
#define CYREG_TCPWM0_GRP1_CNT10_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40588524UL)
#define CYREG_TCPWM0_GRP1_CNT10_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x40588528UL)
#define CYREG_TCPWM0_GRP1_CNT10_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x4058852CUL)
#define CYREG_TCPWM0_GRP1_CNT10_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40588530UL)
#define CYREG_TCPWM0_GRP1_CNT10_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40588540UL)
#define CYREG_TCPWM0_GRP1_CNT10_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40588544UL)
#define CYREG_TCPWM0_GRP1_CNT10_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40588548UL)
#define CYREG_TCPWM0_GRP1_CNT10_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4058854CUL)
#define CYREG_TCPWM0_GRP1_CNT10_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40588550UL)
#define CYREG_TCPWM0_GRP1_CNT10_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40588554UL)
#define CYREG_TCPWM0_GRP1_CNT10_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40588570UL)
#define CYREG_TCPWM0_GRP1_CNT10_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40588574UL)
#define CYREG_TCPWM0_GRP1_CNT10_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40588578UL)
#define CYREG_TCPWM0_GRP1_CNT10_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4058857CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT11)
  */
#define CYREG_TCPWM0_GRP1_CNT11_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40588580UL)
#define CYREG_TCPWM0_GRP1_CNT11_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40588584UL)
#define CYREG_TCPWM0_GRP1_CNT11_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40588588UL)
#define CYREG_TCPWM0_GRP1_CNT11_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40588590UL)
#define CYREG_TCPWM0_GRP1_CNT11_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40588594UL)
#define CYREG_TCPWM0_GRP1_CNT11_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40588598UL)
#define CYREG_TCPWM0_GRP1_CNT11_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4058859CUL)
#define CYREG_TCPWM0_GRP1_CNT11_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405885A0UL)
#define CYREG_TCPWM0_GRP1_CNT11_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405885A4UL)
#define CYREG_TCPWM0_GRP1_CNT11_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x405885A8UL)
#define CYREG_TCPWM0_GRP1_CNT11_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x405885ACUL)
#define CYREG_TCPWM0_GRP1_CNT11_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405885B0UL)
#define CYREG_TCPWM0_GRP1_CNT11_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405885C0UL)
#define CYREG_TCPWM0_GRP1_CNT11_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405885C4UL)
#define CYREG_TCPWM0_GRP1_CNT11_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405885C8UL)
#define CYREG_TCPWM0_GRP1_CNT11_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405885CCUL)
#define CYREG_TCPWM0_GRP1_CNT11_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405885D0UL)
#define CYREG_TCPWM0_GRP1_CNT11_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405885D4UL)
#define CYREG_TCPWM0_GRP1_CNT11_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405885F0UL)
#define CYREG_TCPWM0_GRP1_CNT11_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405885F4UL)
#define CYREG_TCPWM0_GRP1_CNT11_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405885F8UL)
#define CYREG_TCPWM0_GRP1_CNT11_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405885FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT0)
  */
#define CYREG_TCPWM0_GRP2_CNT0_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40590000UL)
#define CYREG_TCPWM0_GRP2_CNT0_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40590004UL)
#define CYREG_TCPWM0_GRP2_CNT0_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40590008UL)
#define CYREG_TCPWM0_GRP2_CNT0_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40590010UL)
#define CYREG_TCPWM0_GRP2_CNT0_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40590014UL)
#define CYREG_TCPWM0_GRP2_CNT0_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40590018UL)
#define CYREG_TCPWM0_GRP2_CNT0_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4059001CUL)
#define CYREG_TCPWM0_GRP2_CNT0_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40590020UL)
#define CYREG_TCPWM0_GRP2_CNT0_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40590024UL)
#define CYREG_TCPWM0_GRP2_CNT0_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40590030UL)
#define CYREG_TCPWM0_GRP2_CNT0_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40590040UL)
#define CYREG_TCPWM0_GRP2_CNT0_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40590044UL)
#define CYREG_TCPWM0_GRP2_CNT0_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40590048UL)
#define CYREG_TCPWM0_GRP2_CNT0_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4059004CUL)
#define CYREG_TCPWM0_GRP2_CNT0_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40590050UL)
#define CYREG_TCPWM0_GRP2_CNT0_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40590054UL)
#define CYREG_TCPWM0_GRP2_CNT0_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40590070UL)
#define CYREG_TCPWM0_GRP2_CNT0_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40590074UL)
#define CYREG_TCPWM0_GRP2_CNT0_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40590078UL)
#define CYREG_TCPWM0_GRP2_CNT0_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4059007CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT1)
  */
#define CYREG_TCPWM0_GRP2_CNT1_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40590080UL)
#define CYREG_TCPWM0_GRP2_CNT1_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40590084UL)
#define CYREG_TCPWM0_GRP2_CNT1_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40590088UL)
#define CYREG_TCPWM0_GRP2_CNT1_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40590090UL)
#define CYREG_TCPWM0_GRP2_CNT1_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40590094UL)
#define CYREG_TCPWM0_GRP2_CNT1_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40590098UL)
#define CYREG_TCPWM0_GRP2_CNT1_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4059009CUL)
#define CYREG_TCPWM0_GRP2_CNT1_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405900A0UL)
#define CYREG_TCPWM0_GRP2_CNT1_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405900A4UL)
#define CYREG_TCPWM0_GRP2_CNT1_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405900B0UL)
#define CYREG_TCPWM0_GRP2_CNT1_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405900C0UL)
#define CYREG_TCPWM0_GRP2_CNT1_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405900C4UL)
#define CYREG_TCPWM0_GRP2_CNT1_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405900C8UL)
#define CYREG_TCPWM0_GRP2_CNT1_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405900CCUL)
#define CYREG_TCPWM0_GRP2_CNT1_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405900D0UL)
#define CYREG_TCPWM0_GRP2_CNT1_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405900D4UL)
#define CYREG_TCPWM0_GRP2_CNT1_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405900F0UL)
#define CYREG_TCPWM0_GRP2_CNT1_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405900F4UL)
#define CYREG_TCPWM0_GRP2_CNT1_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405900F8UL)
#define CYREG_TCPWM0_GRP2_CNT1_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405900FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT2)
  */
#define CYREG_TCPWM0_GRP2_CNT2_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40590100UL)
#define CYREG_TCPWM0_GRP2_CNT2_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40590104UL)
#define CYREG_TCPWM0_GRP2_CNT2_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40590108UL)
#define CYREG_TCPWM0_GRP2_CNT2_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40590110UL)
#define CYREG_TCPWM0_GRP2_CNT2_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40590114UL)
#define CYREG_TCPWM0_GRP2_CNT2_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40590118UL)
#define CYREG_TCPWM0_GRP2_CNT2_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4059011CUL)
#define CYREG_TCPWM0_GRP2_CNT2_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40590120UL)
#define CYREG_TCPWM0_GRP2_CNT2_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40590124UL)
#define CYREG_TCPWM0_GRP2_CNT2_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40590130UL)
#define CYREG_TCPWM0_GRP2_CNT2_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40590140UL)
#define CYREG_TCPWM0_GRP2_CNT2_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40590144UL)
#define CYREG_TCPWM0_GRP2_CNT2_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40590148UL)
#define CYREG_TCPWM0_GRP2_CNT2_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4059014CUL)
#define CYREG_TCPWM0_GRP2_CNT2_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40590150UL)
#define CYREG_TCPWM0_GRP2_CNT2_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40590154UL)
#define CYREG_TCPWM0_GRP2_CNT2_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40590170UL)
#define CYREG_TCPWM0_GRP2_CNT2_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40590174UL)
#define CYREG_TCPWM0_GRP2_CNT2_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40590178UL)
#define CYREG_TCPWM0_GRP2_CNT2_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4059017CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT3)
  */
#define CYREG_TCPWM0_GRP2_CNT3_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40590180UL)
#define CYREG_TCPWM0_GRP2_CNT3_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40590184UL)
#define CYREG_TCPWM0_GRP2_CNT3_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40590188UL)
#define CYREG_TCPWM0_GRP2_CNT3_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40590190UL)
#define CYREG_TCPWM0_GRP2_CNT3_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40590194UL)
#define CYREG_TCPWM0_GRP2_CNT3_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40590198UL)
#define CYREG_TCPWM0_GRP2_CNT3_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4059019CUL)
#define CYREG_TCPWM0_GRP2_CNT3_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405901A0UL)
#define CYREG_TCPWM0_GRP2_CNT3_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405901A4UL)
#define CYREG_TCPWM0_GRP2_CNT3_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405901B0UL)
#define CYREG_TCPWM0_GRP2_CNT3_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405901C0UL)
#define CYREG_TCPWM0_GRP2_CNT3_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405901C4UL)
#define CYREG_TCPWM0_GRP2_CNT3_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405901C8UL)
#define CYREG_TCPWM0_GRP2_CNT3_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405901CCUL)
#define CYREG_TCPWM0_GRP2_CNT3_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405901D0UL)
#define CYREG_TCPWM0_GRP2_CNT3_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405901D4UL)
#define CYREG_TCPWM0_GRP2_CNT3_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405901F0UL)
#define CYREG_TCPWM0_GRP2_CNT3_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405901F4UL)
#define CYREG_TCPWM0_GRP2_CNT3_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405901F8UL)
#define CYREG_TCPWM0_GRP2_CNT3_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405901FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT4)
  */
#define CYREG_TCPWM0_GRP2_CNT4_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40590200UL)
#define CYREG_TCPWM0_GRP2_CNT4_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40590204UL)
#define CYREG_TCPWM0_GRP2_CNT4_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40590208UL)
#define CYREG_TCPWM0_GRP2_CNT4_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40590210UL)
#define CYREG_TCPWM0_GRP2_CNT4_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40590214UL)
#define CYREG_TCPWM0_GRP2_CNT4_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40590218UL)
#define CYREG_TCPWM0_GRP2_CNT4_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4059021CUL)
#define CYREG_TCPWM0_GRP2_CNT4_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40590220UL)
#define CYREG_TCPWM0_GRP2_CNT4_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40590224UL)
#define CYREG_TCPWM0_GRP2_CNT4_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40590230UL)
#define CYREG_TCPWM0_GRP2_CNT4_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40590240UL)
#define CYREG_TCPWM0_GRP2_CNT4_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40590244UL)
#define CYREG_TCPWM0_GRP2_CNT4_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40590248UL)
#define CYREG_TCPWM0_GRP2_CNT4_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4059024CUL)
#define CYREG_TCPWM0_GRP2_CNT4_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40590250UL)
#define CYREG_TCPWM0_GRP2_CNT4_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40590254UL)
#define CYREG_TCPWM0_GRP2_CNT4_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40590270UL)
#define CYREG_TCPWM0_GRP2_CNT4_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40590274UL)
#define CYREG_TCPWM0_GRP2_CNT4_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40590278UL)
#define CYREG_TCPWM0_GRP2_CNT4_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4059027CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT5)
  */
#define CYREG_TCPWM0_GRP2_CNT5_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40590280UL)
#define CYREG_TCPWM0_GRP2_CNT5_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40590284UL)
#define CYREG_TCPWM0_GRP2_CNT5_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40590288UL)
#define CYREG_TCPWM0_GRP2_CNT5_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40590290UL)
#define CYREG_TCPWM0_GRP2_CNT5_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40590294UL)
#define CYREG_TCPWM0_GRP2_CNT5_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40590298UL)
#define CYREG_TCPWM0_GRP2_CNT5_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4059029CUL)
#define CYREG_TCPWM0_GRP2_CNT5_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405902A0UL)
#define CYREG_TCPWM0_GRP2_CNT5_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405902A4UL)
#define CYREG_TCPWM0_GRP2_CNT5_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405902B0UL)
#define CYREG_TCPWM0_GRP2_CNT5_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405902C0UL)
#define CYREG_TCPWM0_GRP2_CNT5_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405902C4UL)
#define CYREG_TCPWM0_GRP2_CNT5_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405902C8UL)
#define CYREG_TCPWM0_GRP2_CNT5_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405902CCUL)
#define CYREG_TCPWM0_GRP2_CNT5_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405902D0UL)
#define CYREG_TCPWM0_GRP2_CNT5_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405902D4UL)
#define CYREG_TCPWM0_GRP2_CNT5_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405902F0UL)
#define CYREG_TCPWM0_GRP2_CNT5_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405902F4UL)
#define CYREG_TCPWM0_GRP2_CNT5_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405902F8UL)
#define CYREG_TCPWM0_GRP2_CNT5_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405902FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT6)
  */
#define CYREG_TCPWM0_GRP2_CNT6_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40590300UL)
#define CYREG_TCPWM0_GRP2_CNT6_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40590304UL)
#define CYREG_TCPWM0_GRP2_CNT6_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40590308UL)
#define CYREG_TCPWM0_GRP2_CNT6_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40590310UL)
#define CYREG_TCPWM0_GRP2_CNT6_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40590314UL)
#define CYREG_TCPWM0_GRP2_CNT6_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40590318UL)
#define CYREG_TCPWM0_GRP2_CNT6_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4059031CUL)
#define CYREG_TCPWM0_GRP2_CNT6_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40590320UL)
#define CYREG_TCPWM0_GRP2_CNT6_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40590324UL)
#define CYREG_TCPWM0_GRP2_CNT6_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40590330UL)
#define CYREG_TCPWM0_GRP2_CNT6_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40590340UL)
#define CYREG_TCPWM0_GRP2_CNT6_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40590344UL)
#define CYREG_TCPWM0_GRP2_CNT6_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40590348UL)
#define CYREG_TCPWM0_GRP2_CNT6_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4059034CUL)
#define CYREG_TCPWM0_GRP2_CNT6_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40590350UL)
#define CYREG_TCPWM0_GRP2_CNT6_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40590354UL)
#define CYREG_TCPWM0_GRP2_CNT6_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40590370UL)
#define CYREG_TCPWM0_GRP2_CNT6_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40590374UL)
#define CYREG_TCPWM0_GRP2_CNT6_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40590378UL)
#define CYREG_TCPWM0_GRP2_CNT6_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4059037CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT7)
  */
#define CYREG_TCPWM0_GRP2_CNT7_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40590380UL)
#define CYREG_TCPWM0_GRP2_CNT7_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40590384UL)
#define CYREG_TCPWM0_GRP2_CNT7_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40590388UL)
#define CYREG_TCPWM0_GRP2_CNT7_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40590390UL)
#define CYREG_TCPWM0_GRP2_CNT7_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40590394UL)
#define CYREG_TCPWM0_GRP2_CNT7_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40590398UL)
#define CYREG_TCPWM0_GRP2_CNT7_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4059039CUL)
#define CYREG_TCPWM0_GRP2_CNT7_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x405903A0UL)
#define CYREG_TCPWM0_GRP2_CNT7_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x405903A4UL)
#define CYREG_TCPWM0_GRP2_CNT7_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x405903B0UL)
#define CYREG_TCPWM0_GRP2_CNT7_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x405903C0UL)
#define CYREG_TCPWM0_GRP2_CNT7_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x405903C4UL)
#define CYREG_TCPWM0_GRP2_CNT7_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x405903C8UL)
#define CYREG_TCPWM0_GRP2_CNT7_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x405903CCUL)
#define CYREG_TCPWM0_GRP2_CNT7_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x405903D0UL)
#define CYREG_TCPWM0_GRP2_CNT7_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x405903D4UL)
#define CYREG_TCPWM0_GRP2_CNT7_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x405903F0UL)
#define CYREG_TCPWM0_GRP2_CNT7_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x405903F4UL)
#define CYREG_TCPWM0_GRP2_CNT7_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x405903F8UL)
#define CYREG_TCPWM0_GRP2_CNT7_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x405903FCUL)

#endif /* _CYREG_TCPWM_H_ */


/* [] END OF FILE */
